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changes.mady.by.user John Hartfiel

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NameDirectionPinDescription
1.8V_EN  / EN_1V8out106Power
5V_EN          115(currently controlled via S4-4) / currently_not_used
C_TCK          131JTAG J28 (XMOD2) / internal currently_not_used
C_TDO          137JTAG J28 (XMOD2) / internal currently_not_used
C_TDO1         136JTAG J28 (XMOD2) / internal currently_not_used
C_TMS          130JTAG J28 (XMOD2) / internal currently_not_used
CLK_A / AUD_CLK        out1AUDIO U3 CLK
CLK_CPLD / MEMS_CLKINin128U25 24,576MHz
DONE          in67PS Done / currently_not_used
EN_DDR        out86Enable DDR Power
EN_FMC / FMC_EN    out104FMC
EN_FPD        out81Enable PS FPD Power
EN_GT_L       out77Enable  GT Power
EN_GT_R       out93 Enable GT Power
EN_LPD        out84Enable PS LPL Power
EN_PL         out95Enable PL Power
EN_PLL_PWR    out78Enable SI5345 Power
EN_PSGT / EN_PSGTR      out75Enable  PS GT Power
ERR_OUT  / ERROR    in70PS Error Out / readable via RGIO / currently_not_used
ERR_STATUS  / ERROR_STATin69PS Error Status / readable via RGIO / currently_not_used
F1PWM         out121FAN1
F1SENSE       in125FAN1
FAN_FMC_EN  / FMC_EN    FAN_ENout132FMC FAN
FMC_PG_C2M     141FMC / currently_not_used
HD_LED_N / HDLED_Nout112J10 HD LED
HD_LED_P / HDLED_Pout110J10 HD LED
HDIO_SC0 / SC0in32FPGA IO
HDIO_SC1 / SC1in33FPGA IO
HDIO_SC2 / SC2in34FPGA IO
HDIO_SC3 / SC3out35FPGA IO
HDIO_SC4 / SC4out25FPGA IO
HDIO_SC5 / SC5out26FPGA IO
HDIO_SC6 / SC6in27FPGA IO / CLK
HDIO_SC7 / SC7     in28FPGA IO
I2C_SCL / SCLin50I2C / currently_not_used
I2C_SDA / SCAin52I2C / currently_not_used
INIT_B / INITin68PS init B / currently_not_used
JTAGENB 
120external Pin for CPLD Firmware Update 
LP_GOOD  / PG_LPD    in83LP Power Good / currently_not_used
MIO24          38MIO / currently_not_used
MIO25          39MIO / currently_not_used
MIO30          48MIO / currently_not_used
MIO31         in49MIO / currently_not_used
MIO32           40MIO / currently_not_used
MIO33           41MIO / currently_not_used
MIO34           42MIO / currently_not_used
MIO35           43MIO / currently_not_used
MIO36           44MIO / currently_not_used
MIO37           45MIO / currently_not_used
MIO40           54MIO / currently_not_used
MIO41          55MIO / currently_not_used
MIO42         out60FPGA UART RX
MIO43         in61FPGA UART TX
MIO44          47/ currently_not_used
MOD_EN        out119Module Power 3.3V Enable
MODE0         out6Boot Mode
MODE1         out9Boot Mode
MODE2         out10Boot Mode
MODE3         out11Boot Mode
MR / MRESETn           out92PS Reset
PCI_SFP_EN    out76SFP
PER_EN        out117Baseboard Power 3.3V Enable
PERST / PERSTn        out139PCIE Resetn
PG_DDR        in91Power Good / readable via RGIO / currently_not_used
PG_FPD        in85Power Good / readable via RGIO / currently_not_used
PG_GT_L       in96Power Good / readable via RGIO / currently_not_used
PG_GT_R       in94Power Good / readable via RGIO / currently_not_used
PG_PL         in82Power Good / readable via RGIO / currently_not_used
PG_PLL_1V8 / PG_PLLin73Power Good / readable via RGIO / currently_not_used
PG_PSGT       in74Power Good / readable via RGIO / currently_not_used
PLL_LOLN / PLL_LOL     in58Module U5 Si5345 / readable via RGIO / currently_not_used
PLL_RST / PLL_RSTn      out56Module U5 Si5345
PLL_SEL0      out57Module U5 Si5345
PLL_SEL1      out59Module U5 Si5345
POK_1V8        107Power / currently_not_used
POK_FMC        in99FMC Power/ readable via RGIO / currently_not_used
PROG_B        inout71PS_PROG_B
PSON          out105ATX J20 PS_ON_N
PWR_BTN       in113Power Button S1 or J10
PWRLED_N / LED_Nout111J10 PWR
PWRLED_P / LED_Pout109J10 PWR
PWROK         in100ATX J20 PWROKPWROK  / readable via RGIO
RST_BTN       in114Reset Button S2 or J10
S_1 127Beeper/ currently_not_used
SC_IO0 / X0out12Master-Slave SC-Communication / Power Reset
SC_IO1 / X1out13Master-Slave SC-Communication / Power Reset
SC_IO2 / X2out14Master-Slave SC-Communication / currently_not_used
SC_IO3 / X3out20Master-Slave SC-Communication / currently_not_used
SC_IO4 / X4in21Master-Slave SC-Communication / currently_not_used
SC_IO5 / X5in22Master-Slave SC-Communication / currently_not_used
SC_IO6 / X6in23Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable)
SC_IO7 / X7       in24Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable)
SC_IO8 / dummy       126/ currently_not_used / ! not available on PCB REV2 !
SC2_SW1       in133S5-1 / Boot Mode Selection / readable via RGIO
SC2_SW2       in138S5-2 / Boot Mode Selection / readable via RGIO
SD_A_EN       out140Micro SD
SD_B_EN       out122MMC SD
SD_CD / SD_CD_OUTout65SD Card detect to FPGA
SD_CD_B       in143MMC SD / readable via RGIO
SD_CD_S       in142Micro SD / readable via RGIO
SEL_SD / SD_SELout62Select SD
SRST_B / SRSTn      out19PS_SRST_B
STAT_LED2 / LED2out98LED D6 Green
STAT_LED3 / LED3out97LED D7 Red
XMOD2_A / XMOD_TXD     out5J12 (XMOD 1)
XMOD2_B / XMOD_RXDin4J12 (XMOD 1)
XMOD2_E  / XMOD_LED   out3J12 (XMOD 1)
XMOD2_G  / XMOD_BTNin2J12 (XMOD 1) / readable via RGIO

 

Functional Description

JTAG

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NameDescription
PLL_RSTnnot RGPIO (0) when active else '1'
SRSTnnot RGPIO (1) when active else  '1'
MRESETnnot RGPIO (2) when active else RST_BTN and PSON and "PS reboot via FSBL"
PERSTnnot RGPIO (31) and MIO31 when active else PWR_BTN rst_btn_i and MIO31
Master CPLD Resetwith PSON and Reset Button over CPLD interconnect.
PS reboot via FSBLReboot possible over FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)

Boot Mode

S4-1S4-2Description
ONONDefault, boot from SD/eMMC or SPI Flash if no SD is detected
OFFONBoot mode  PJTAG0
ONOFFBoot from eMMC
OFFOFFBoot mode main  JTAG

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UART

XMOD_TXD is sourced by MIO43 and MIO42 by XMOD_RXD.

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unused
RGPIO Pin to FPGAValue
0SW1
1SW2
2RSTXMOD_BTN
3PWR_BTNForce FSBL reboot done
4SD_CD_S
5SD_CD_B
6F1SENSEError
7PWROKERR_STAT
11-8XMOD_BTN
9-19unused
20PLL_LOL
Boot Mode
12PG_LPD
13PG_DDR
14PG_FPD
15PG_PSGT
16PG_GT_L
17PG_GT_R
18POK_FMC
19DET_POWROK
20PWROK
21PG_PL
22PG_PLL
23PLL_LOL21-23
24-27reserved
28-31Interface detection
RGPIO Pin from FPGAValue
0PLL_RSTn
1SRSTnPERSTn
2MRESETn
3PERSTn
4PROG_BFMC_FAN_EN
5LED2
6LED3
7LED_N
8LED_P
9HDLED_N
10HDLED_P11FMC_FAN_EN
12-23unused
24-27reserved
28-31Interface detection

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Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV04 to REV05

  • PS reboot via FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)
  • SD Boot from micoSD only if switch S4-1/-2 is selected to ON
  • RGPIO connection

Older Revision (PCB REV03) to CPLD REV04

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.


 

REV04REV05REV02, REV03, REV04 

Page info
modified-users
modified-users

Revision 05 working in process
2017-02-08v.19REV04REV02, REV03, REV04 Revision 04 finished
2016-04-11

v.1

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Page info
created-user
created-user

Initial release
 All  
 

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