Page History
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FPGA Bank | Zynq Pin | Signal Name | Connected To |
---|---|---|---|
35 | F13 | DSI_D0_R_N | DSI display connector J4 |
35 | F14 | DSI_D0_R_P | DSI display connector J4 |
35 | F12 | DSI_D1_R_N | DSI display connector J4 |
35 | E13 | DSI_D1_R_P | DSI display connector J4 |
35 | E11 | DSI_C_R_N | DSI display connector J4 |
35 | E12 | DSI_C_R_P | DSI display connector J4 |
See also section FPGA IO Banks Pin Mapping, pins DSI_XA and DSI_XB.
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Overview
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