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Table of Contents

Table of Contents
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Overview

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Refer to https://shopwiki.trenz-electronic.de/dedisplay/Download/?path=Trenz_Electronic/PD/TE0715+TRM for downloadableonline version of this manual and additional technical documentation of the product.
 

The Trenz Electronic ... TE0720 is an industrial-grade ... based on ...

Block diagram

Put your block diagram here...

Main components

Put top and bottom pics with labels of the real PCB here...

Add description list of PCB labels here...

Key features

List key features here, like FPGA type, amount and type of RAM, type of flash, etc.

SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020) with up to 1 GB of DDR3/L SDRAM, 32MB of SPI flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. See also Variants Currently in Production section.

Key Features

  • Xilinx XC7Z SoC (XC7Z020)
    - Processing System: Dual ARM Cortex-A9
         Unified 512 KByte L2 cache
         256 KByte on-chip memory
         54 multiplexed I/O pins (MIOs)
    - Programmable Logic: Artix-7 FPGA
         85 K logic cells
         560 KByte extensible block RAM (140x 36 Kbit BRAM blocks)
         220 programmable DSP slices
         Dual 12-bit 1Msps AD converter
         200 I/O pins (SelectIO interfaces)
  • System Controller CPLD (Lattice LCMXO2-1200HC)
  • 1 GByte DDR3/L memory, 2 x 256 Mbit x 16 (32-bit wide)
  • 32 MByte Quad SPI Flash memory
  • Gigabit Ethernet transceiver PHY (Marvell 88E1512)
  • Highly Integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK)
  • 3-axis accelerometer and 3-axis magnetometer (ST Microelectronics LSM303DTR) (Not installed!)
  • Real time clock with embedded crystal (Intersil ISL12020M): ±5ppm accuracy
  • Up to 32 GByte eMMC, usually 4 GByte, depends on module variant and assembly option
  • User LED 1 (Green), user LED 2 (Red), user LED 3 - FPGA DONE (Green)
  • 1.5A, PowerSoC DC-DC step-down converter (Enpirion EP53F8QI) for 1.8V power supply
  • 1.5A, PowerSoC DC-DC step-down converter (Enpirion EP53F8QI) for 1.5V power supply
  • 4A PowerSoC DC-DC step-down converter (Enpirion EN6347) for 1.0V power supply
  • Trenz 4 x 5 module socket connector (3 x Samtec LSHM series connectors)

...

Additional assembly options are available for cost or performance optimization upon request.

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Block Diagram

Image Added

Components and connections marked with dashed lines are optional or may be missing on some module variants, please contact us for additional information.

Main Components

 Image Added Image Added

  1. Xilinx Zynq XC7Z SoC, U5
  2. 4 Gbit DDR3/L SDRAM, U13
  3. 4 Gbit DDR3/L SDRAM, U12
  4. Low-power RTC with battery backed SRAM, U20
  5. 32 MByte Quad SPI Flash memory, U7
  6. Red LED (LED1), D5
  7. Green LED (LED2), D2
  8. System Controller CPLD, U19
  9. eMMC NAND Flash, U15
  10. 4A high-efficiency PowerSoC DC-DC step-down Converter (1V), U1
  11. Green LED (DONE), D4
  12. B2B connector Samtec Razor Beam™ LSHM-130, JM3
  13. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  14. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  15. Hi-speed USB 2.0 ULPI transceiver, U18
  16. Gigabit Ethernet (GbE) transceiver, U8
  17. Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
  18. Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
  19. Low-dropout regulator (VBATT), U24
  20. DDR termination regulator, U4
  21. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
  22. Atmel CryptoAuthentication chip, U10
  23. 2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
  24. Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
  25. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
  26. 3A PFET load switch with configurable slew rate (3.3V), Q1

Initial Delivery State

Storage device name

IC

Content

Notes

 

 

Quad SPI Flash

U7

Empty

-
eMMC NAND FlashU15Empty-
11AA02E48T EEPROMU17

Pre-programmed globally unique, 48-bit node address (MAC)

-
System Controller CPLDU19Standard firmware.Download firmware
 

Signals, Interfaces and Pins

Board to Board (B2B) I/

...

Os

I/O signals connected to the SoC's I/O IO bank and B2B connector: 

BankTypeB2B ConnectorI/O Signal CountVoltageNotes
13GPIOJM248 I/Os, 24 LVDS pairsVCCIO13 
13GPIOJM22 I/OsVCCIO13B13_IO0 and B13_IO25
33GPIOJM218 I/Os, 9 LVDS pairsVCCIO33 
34GPIOJM336 I/Os, 18 LVDS pairsVCCIO34 
35GPIOJM148 I/Os, 24 LVDS pairsVCCIO35 
500MIOJM18 MIOs3.3V 
501MIOJM16 MIOs1.8V 

For detailed information about the pin-out, please refer to the Pin-out Tables. tables. 

JTAG Interface

JTAG access to the Xilinx Zynq and to the System Controller CPLD is provided through B2B connector JM2.

JTAG Signal

B2B Connector Pin

TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99
Note
JTAGMODE pin 89 in B2B connector JM1 is used to select which device is accessible. Low - Xilinx Zynq, High - System Controller CPLD.

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System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
RESINInputReset inputActive low reset input, default mapping forces POR_B reset to Zynq PS.
PGOODOutputPower goodActive high when all on-module power supplies are working properly.
MODEInputBoot modeForce low for boot from the SD card. Latched at power-on only, not during soft reset!
EN1InputPower enableHigh enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high.
NOSEQInputPower sequencingForces the 1.0V and 1.8V DC-DC converters always ON when high.
JTAGMODEInputJTAG selectKeep low for FPGA JTAG access.

On-board LEDs

LEDColorConnected toDescription and Notes
D2GreenLED1Controlled by System Controller CPLD firmware.
D4GreenDONE 
D5RedLED2Controlled by System Controller CPLD firmware.

Clocking

Clock SignalFrequencyICFPGANotes

PS-CLK

33.333333 MHz

U6

PS_CLK_500

PS subsystem main clock.

OTG-RCLK

52.000000 MHz

U14

-

USB3320C reference clock.

ETH-CLK25.000000 MHzU9-88E1512 reference clock.

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Default MIO Mapping

MIOFunctionB2B PinNotes MIOFunctionB2B PinNotes
0GPIOJM1-87- 16..27ETH0-RGMII
1QSPI0-SPI-CS 28..39USB0-ULPI
2QSPI0-SPI-DQ0 40SD0JM1-27B2B
3QSPI0-SPI-DQ1 41SD0JM1-25B2B
4QSPI0-SPI-DQ2 42SD0JM1-23B2B
5QSPI0-SPI-DQ3 43SD0JM1-21B2B
6QSPI0-SPI-SCK 44SD0JM1-19B2B
7GPIO-SC CPLD pin P11 45SD0JM1-17B2B
8--3.3V 46SD1-MMC-D0
9-JM1-91B2B 47SD1-MMC-CMD
10-JM1-95B2B 48SD1-MMC-CLK
11-JM1-93B2B 49SD1-MMC-D1
12-JM1-99B2B 50SD1-MMC-D2
13-JM1-97B2B 51SD1-MMC-D3
14-JM1-92B2B 52ETH0-MDC
15-JM1-85B2B 53ETH0-MDIO


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Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).

Ethernet PHY connection

 
PHY PinZynq PSPLNotes   Notes
MDCMIO52Routed to System Controller CPLD pin L14.
MDIOMIO53Routed to System Controller CPLD pin K14.
LED0-Routed to System Controller CPLD pin F14.
LED1-Routed to System Controller CPLD pin D12.
LED2/Interrupt-Routed to System Controller CPLD pin C13.
CONFIG-Routed to System Controller CPLD pin C14.
RESETnMIO50-
RGMIIMIO16..MIO27-
SGMII-Routed to B2B connector JM3.
MDI-Routed to B2B connector JM1.

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USB Interface

USB PHY is provided with ...by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and reference clock input of the PHY is supplied from the on-board 52.000000 MHz oscillator (U14).

USB PHY connection

USB PHY PinZYNQ PinSC CPLD
PHY Pin
PinB2B NameNotes
REFCLK---52.000000 MHz reference clock from on-board oscillator (U14).
REFSEL0..2---Reference clock frequency select, all set to GND selects 52.000000 MHz.
RESETB-B14, bank 1-Active low reset.
CLKOUTMIO36--ULPI output clock mode.
DP, DM- OTG-D_P, OTG-D_NUSB data lines.
CPEN- 
 
VBUS_V_ENExternal USB power switch active high enable signal.
VBUS--USB-VBUSConnect to USB VBUS via a series of resistors, see reference schematics.
ID--OTG-IDFor A-device connect to the ground, for B-device leave floating.
SPK_L-M5, bank 2-In USB audio mode a switch connects the DM pin to the SPK_L pin.
SPK_R-M8, bank 2-In USB audio mode a switch connects the DP pin to the SPK_R pin.
 

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host host or Device device modes. A Mini mini-USB connector can be used for USB Device device mode. A micro-USB Micro connector can be used for Device device mode, OTG Mode mode or Host Modehost mode.

I2C Interface

On-board I2C I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices the System Controller CPLD, device slave addresses are listed in the table below:

I2C DeviceI2C AddressICI2C DeviceI2C AdressNotes
 ISL12020M RTC 0x6F 

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

...

JTAG Signal

...

B2B Connector Pin

...

Note
JTAGEN pin in B2B connector ... should be kept low or grounded for normal operation.

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

...

U20RTC registers.
ISL12020M SRAM0x57U20Battery backed RAM in RTC IC.
LSM303D0x1DU22Optional, not soldered on current production variants.

Boot Process

By default the TE-0720

Boot Modes

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

MODE Signal State

Boot Mode

high High or open

SD Card

low Low or connected to the ground

QSPI

LED's

...

On-board Peripherals

Processing System (PS) Peripherals

NameICIDPS7MIO BankMIONotes
SPI FlashS25FL256SAGBHI20U14QSPI0MIO1..MIO6 

Clocking

...

PS CLK

...

33.3333 Mhz

...

 

...

PS_CLK

...

PS subsystem main clock.

...

GT REFCLK1

...

125 Mhz

...

 

...

Gigabit Ethernet88E1512U8ETH0501

MIO16..27

MIO52..53

MIO52 and MIO53 are also connected to the System Controller CPLD.
USB OTGUSB3320CU18USB0501MIO28..39 
SPI FlashS25FL256SAGBHI20U7QSPI0500MIO1..6 
eMMC FlashMTFC4GMVEA-4M IT1)U15SD1501MIO46..51 

1) Different make and model may be installed on different module variants.

RTC - Real Time Clock

An temperature compensated  ... compensated Intersil ISL12020M is used for Real Time Clock (U20). Battery voltage must be supplied to the module from the baseboard. .

PLL - Phase-Locked Loop

There is a I2C programmable clock generator ... chip on the ...

PLL connection

...

Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

MAC-Address EEPROM

A ... Microchip 2Kbit 11AA02E48 serial EEPROM (U..U17) is used which contains a connected to the System Controller CPLD and contains globally unique 48-bit node address , that which is compatible with EUI-48(TM) and EUI-64(TM) specificationTM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.

Power and Power-On

...

Sequence

Power Supply

Power supply with minimum current capability of ...A 3A for system startup is recommended.

Power Consumption

Power Input PinMax Typical Current
VINTBD*
3.3VINTBD*

 * TBD - To Be Determined soon with reference design setup.

Power-On Sequence

For highest efficiency of the on-board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails.

 

Power Rails

...

Voltages on B2B-

Connectors

...

B2B

...

B2B

...

B2B

...

Input/

Output

...

Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See also Xilinx datasheet DS187 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0720 module.

Power Rails

B2B Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Note
VIN1, 3, 52, 4, 6, 8InputSupply voltage from baseboard.
3.3VIN13, 1591InputSupply voltage from baseboard. JM2-91 is VREF_JTAG.
VCCIO359, 11-InputHigh range bank voltage from baseboard.
VCCIO33-5InputHigh range bank voltage from baseboard.
VCCIO13-7, 9InputHigh range bank voltage from baseboard.
VCCIO34-1, 3InputHigh range bank voltage from baseboard.
VBAT_IN79-InputRTC battery-buffer supply voltage.
3.3V-10, 12OutputInternal 3.3V voltage level.
1.8V39-OutputInternal 1.8V voltage level.
1.5V 1)-19OutputInternal 1.5V voltage level.

1) In case of module variant of TE0720-03-L1IF which uses Xilinx Zynq XC7Z020-L1CLG484I chip with lower power consumption, power rails named 1.5V and VCCO_DDR_502 voltage is actually 1.35V. To achieve this, a resistor with different value is used for R4 (see schematics of the TE0720-03-L1IF for more information).

...

Bank Voltages

Bank          

Schematic
Schematics Name

Voltage

TE0715-xx-15        

TE0715-xx-30           

     

Board to Board Connectors

... put some B2B related information here if you have them ...

...

Notes
5003.3V, VCCO_MIO0_5003.3V 
5011.8V, VCCO_MIO1_5011.8V 
5021.5V, VCCO_DDR_5021.5V 
0 Config3.3V3.3V 
13 HRVCCO131.2V to 3.3VSupplied by the baseboard.
33 HRVCCIO331.2V to 3.3VSupplied by the baseboard.
34 HRVCCIO341.2V to 3.3VSupplied by the baseboard.
35 HRVCCIO351.2V to 3.3V

Supplied by the baseboard.

Board to Board Connectors

Include Page
IN:Samtec LSHM
IN:Samtec LSHM

Variants Currently in Production

Module VariantZynq SoC

RAM

eMMC

Size

Temperature

Range

B2B Connector

Height

TE0720-03-2IFXC7Z020-2CLG484I1 GByte4 GByteIndustrial4.0 mm
TE0720-03-2IFC3XC7Z020-2CLG484I1 GByte4 GByteIndustrial2.5 mm
TE0720-03-2IFC8XC7Z020-2CLG484I1 GByte32 GByteIndustrial4.0 mm
TE0720-03-L1IF XC7Z020-L1CLG484I512 MByte4 GByteIndustrial4.0 mm
TE0720-03-1CFXC7Z020-1CLG484C1 GByte4 GByteCommercial4.0 mm
TE0720-03-1CRXC7Z020-1CLG484C256 MByte-Commercial4.0 mm
TE0720-03-14S-1CXC7Z014S-1CLG484C1 GByte4 GByteCommercial4.0 mm
TE0720-03-1QFXA7Z020-1CLG484Q1 GByte4 GByteAutomotive4.0 mm

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

  

V

-

Storage temperature

-40

+85

°C

-

Recommended Operating Conditions

-0.36.5

V

EP53F8QI datasheet.
3.3VIN supply voltage-0.13.75VTPS27082L and LCMXO2-1200HC datasheets.
Supply voltage for PS MIO banks-0.53.6VSee Xilinx DS187 datasheet.
I/O input voltage for MIO banks-0.4VCCO_MIO + 0.55V

See Xilinx DS187 datasheet.

(VCCO_MIO0_500, VCCO_MIO1_501)

Supply voltage for HR I/Os banks-0.53.6V

See Xilinx DS187 datasheet.

(VCCIO13, VCCIO33, VCCIO34, VCCIO35)

I/O input voltage for HR I/O banks-0.4VCCIO + 0.55VSee Xilinx DS187 datasheet.

Storage temperature

-40

+85

°C

-
Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed-55+100°CNB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C.
ParameterMinMaxUnitsReference DocumentVIN supply voltage    
Note
Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

  • Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ... mm.

  • PCB thickness: ... mm.

  • Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

 All dimensions are given in mm.

Note
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage2.55.5VEN6347QI and EP53F8QI datasheets.
3.3VIN supply voltage3.1353.465V3.3V +/- 5%.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.20VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.

...

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

... g - Plain ...

Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

  • PCB thickness: 1.6 mm.

  • Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

Image Added     Image Added

Weight

ca 23 g - Plain module... g - Set of bolts and nuts

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation linkLink
2015-10-1203  TE0720-03
-02  TE0720-02
-

01

Prototypes

  

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Put pic of PCB silk screen here showing model and revision ...

Document Change History

Date

Revision

Contributors

Description

20162017-1106-3001
Jan Kumann
 
Initial Documentdocument.

Disclaimer

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