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| Switch | Signal Name | ON | OFF | Notes |
|---|---|---|---|---|
| S1-1 | - | - | - | Not connected. |
| S1-2 | PROGMODE | JTAG enabled for programing SoM's Zynq-SoC. | JTAG enabled for programing SoM's CPLD. | - |
| S1-3 | MODE | Drive SoM SC CPLD pin 'MODE' low. | Leave SoM SC CPLD pin 'MODE' open. | Boot mode configuration, if supported by SoM. (Depends also on SoM's SC CPLD firmware). |
| S1-4 | EN1 | Drive SoM SC CPLD pin 'EN1' low. | Drive SoM SC CPLD pin 'EN1' high. | Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware). Note: Power-on sequence will be intermitted when S1-4 is set to OFF and functionality is supported by SoM. |
Connector J5 and J6
On the TE0706-02 carrier board there is one 50-pin IDC male connector socket available for access to the SoM's PL IO-bank-pins. 32 module's IO-pins are also usable as 18 LVDS-pairs and 8 IO's as single-ended (MIO0, MIO9 - MIO 15), which give access to the MIO0-bank of the Zynq-module if mounted. The available VCCIOs on this connector are 3.3V and M3.3VOUT from module. This connector gives also access to the LEDs of MagJack J2.
Place-holder J6 provides the possibility to mount and solder a VG96 backplane connector te get access to SoM's PL IO-bank-pins. 82 IO's are available on this connector, which are also usable as up to 41 LVDS-pairs. The available VCCIOs on this connector are 3.3V and M3.3VOUT from module and also the selectable PL I/O bank supply-voltages VCCIOA and VCCIOC. The pins A1, A2 are connected to the barrel jack for 5 V Power supply input.
On the TE0706-02 carrier board there is one 50-pin IDC male connector socket and J5 and a place-holder (VG96-Connector solder pads) J6 to provides access to SoM's PL IO-bank-pins. With this user interfaces, a large quantity of IO's are also usable as LVDS-pairs and different VCCIO's are available to operate the IO's properly.
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| Connector Designator | Connector Type | Count of IO's | Count of LVDS Pairs | Available VCCIO's | Interfaces |
|---|---|---|---|---|---|
| J5 | 50-pin IDC male | 40 | 16 | 3.3V, | access to the LEDs of MagJack J2 access to the MIO0-bank of the Zynq module |
| J6 | VG96-Connector | 82 | 41 | 3.3V, | PGOOD-, NOSEQ-Signal of SC-CPLD of mounted 4 x 5 SoM |
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