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Table of Contents

Table of Contents

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • 2x Non-isolated power connectors
  • 2x  RJ45 Transceivers
  • 3x Board to Board (B2B) Connectors
  • 2x XMOD JTAG/UART Adaptor
  • 4x SMA Coaxial Connectors
  • DIP Switch
  • 3 x Samtec ASP-122953-01 160-pin stackable, compatible with TE078x
  • 2 mm MC LB2-A Soldered Connector for power supply (12V input)
  • 4 SMA connectors for MGT
  • 2 x 12 pin headers for XMOD
  • 1 x DIP switch for modules CPLD Access
  • 2 x RJ45 Connector
  • USB A Stacked Connector 
  • Equipped with two TE0790 XMOD FTDI JTAG adapters
  • Voltage regulators
  • Dimension: 115 x 115 mm

Block Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTExxxx TEBT0782 block diagram


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Main Components

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titleTExxxx TEBT0782 main components


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  1. RJ45 Transceivers, J1-J2
  2. USB A Stacked, U7
  3. XMOD JTAG/UART BaseAdapter, J7
  4. JTAG CPLD Adapter -J8
  5. 2 Line Common Mode Choke, J10
  6. Non-isolated power jack (VIN), J9-J11
  7. DIP Switch, S1
  8. SMA Coxial Connectors (MGT_TX), J3-J4
  9. SMA Coxial Connectors (MGT_RX), J5-, J3...J6
  10. Board to Board ConnectorsConnector, JB1...JB3
  11. Board to Board Connector, JB3
  12. Board to Board Connector, JB2

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

-

-

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Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The general Reset is provided through button S1 on TE0790 XMOD J7.

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titleBoot Reset process.

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MODE

Signal

State

B2B
Boot Mode
Note
Notes

RESIN

XMOD_B

JBC3-
135
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titleReset process.
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Signal

B2BNote

RESIN

JBC3-130

Signals, Interfaces and Pins

130Board Reset


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator Designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

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titleGeneral PL I/O to B2B connectors information

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FPGA Bank
B2B ConnectorInterfaceNumber of I/O
Signal Count
Voltage Level
Notes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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titleJTAG pins connection

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JTAG Signal

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B2B Connector

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MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

JB1








RJ45, J1B-J1C1 Differential pair, 2 Single EndedYellow, Green LEDs
RJ45, J1A4 Differential pair, 8 Single EndedPHY1 MDIO
RJ45, J2B-J2C1 Differential pair, 2 Single EndedYellow, Green LEDs
RJ45, J2A4 Differential pair, 8 Single EndedPHY2 MDIO
TE0790 Base, J84 Single Ended
TE0790 Base, J71 Single Ended
USB A Stacked, U72 Single EndedUSB
Power Switch, U12 Single Ended
SMD Line Filter, L61 Differential pair, 2 Single EndedUSB1_D
SMD Line Filter, L71 Differential pair, 2 Single EndedUSB2_D
ESD protection diode, U51 Single EndedUSB1_VBUS
ESD protection diode, U81 Single EndedUSB2_VBUS
JB2

Module TE078x FPGA, Bank 111-11216 Differential pair, 32 Single EndedMGT_RX8...15, MGT_TX8...15
Module TE078x FPGA, Bank 341 Differential pair, 2 Single Ended

J1_B34_VRP, J1_B34_VRN

Module TE078x FPGA, Bank 341 Differential pair, 2 Single EndedJ1_B33_VRP, J1_B33_VRN
JB3



TE0790 Base, J84 Single EndedM_TCK, M_TMS, M_TDO, M_TDI
TE0790 Base, J7

4 Single Ended

2 Single Ended

1 Single Ended

TCK, TMS, TDO, TDI

UART RX/TX

RESIN

DIP Switch, S1-A1 Single EndedJTAGENB
SMA Coaxial, J3...62 Differential pair, 4 Single EndedMGT_RX0, MGT_TX0
Module TE0782...4 FPGA, Bank 109-11016 Differential pair, 32 Single EndedMGT_RX1...7, MGT_TX0...7


XMOD Pin Header

JTAG/UART to Module SoC/FPGA

JTAG access to the TE078x SoM is available through B2B connector JB3.  JTAG access is provided by TE0790 XMOD Adapter on Pin Header J7.

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titleJTAG pins connection

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Designator
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JTAG Interface Pins

Signal Name

B2B Connector

Chip/Interface

Notes