Page History
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The pin-assignment of the SFP connector is in detail as fellows:
| SFP+ pinPin | SFP+ pin net-namePin Schematic Name | B2B Connector | Note |
|---|---|---|---|
| Transmit Data + (pin 18) | MGT_TX2_P | JM1-14 | - |
| Transmit Data - (pin 19) | MGT_TX2_N | JM1-16 | - |
| Receive Data + (pin 13) | MGT_RX2_P | JM1-7 | - |
| Receive Data - (pin 12) | MGT_RX2_N | JM1-9 | - |
| Transmit Fault (pin 2) | SFP0_TX_FAULT | JM2-42 | - |
| Transmit disable (pin 3) | SFP0_TX_DIS | JM2-44 | - |
| MOD-DEF2 (pin 4) | SFP0_SDA | JM2-46 | 3.3V pull-up, (usable as I²C-SDA) |
| MOD-DEF1 (pin 5) | SFP0_SCL | JM2-48 | 3.3V pull-up, (usable as I²C-SCL) |
| MOD-DEF0 (pin 6) | SFP0_M0DEF0 | JM2-40 | - |
| RS0 (pin 7) | SFP0_RS0 | JM2-38 | - |
| LOS (pin 8) | SFP0_LOS | JM2-34 | - |
| RS1 (pin 9) | SFP0_RS1 | JM2-32 | - |
Table 1: SFP+ connector pin-assignment
Ultra
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Small SMT
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Coaxial Connectors
4 HIROSE Ultra Small Surface Mount Coaxial Connectors are on the base-board available for access to the MGT-lange 3 of the SoM with data transmission rates up to 6 Gbit/s. The connectors have the manufacturer designation 'U.FL-R-SMT-1', mating hight: 2.4 mm.
Each conductor of the RX- and TX-LVDS-pair is routed to one coaxial connector:
| Connector designatorDesignator | connected withConnected to | B2B Connector |
|---|---|---|
| J5 | MGT_TX3_P | JM1-8 |
| J6 | MGT_TX3_N | JM1-10 |
| J7 | MGT_RX3_P | JM1-1 |
| J8 | MGT_RX3_N | JM1-3 |
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This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, so the XMOD-FT2232H adapter-board TE0790 can be used in conjunction with the carried board to program the mounted SoM via USB interface.
| JX1-pin | JX1-pin net-nameSchematic Name | B2B Connector | J3-pin | J3 pin net -namein Schematic Name | B2B Connector | |
|---|---|---|---|---|---|---|
| C (pin 4) | TCK | JM1-90 | 4 | TCK | JM1-90 | |
| D (pin 8) | TDO | JM1-88 | 8 | TDO | JM1-88 | |
| F (pin 10) | TDI | JM1-86 | 10 | TDI | JM1-86 | |
| H (pin 12) | TMS | JM1-92 | 12 | TMS | JM1-92 | |
| A (pin 3) | B14_L25 (usable as UART RX/TX-line) | JM2-97 | 3 | B14_L25 | JM2-97 (usable as UART RX/TX-line) | |
| B (pin 7) | B14_L0 (usable as UART RX/TX-line) | JM2-99 | 7 | B14_L0 | JM2-99 (usable as UART RX/TX-line) | |
| E (pin 9) | BOOTMODE | JM2-100 | 9 | BOOTMODE | JM2-100 | |
| G (pin 11) | PROG_B | JM1-94 | 11 | PROG_B | JM1-94 | |
| - | - | - | 13 | XADC_P | JM1-25 (ADC_P, decoupling capacitator 100 nF) | |
| - | - | - | 14 | XADC_N | JM1-27 (ADC_N, decoupling capacitator 100 nF) | |
| - | - | - | 15 | CLK0_P | JM1-2 (MGT_CLK0_P, 1KΩ serial resistor) | |
| - | - | - | 16 | CLK0_N | JM1-4 (MGT_CLK0_N, 1KΩ serial resistor) |
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Three LEDs are present on the TEBB0714 base-board with following functionality:
| LED designatorDesignator | color | Color | Pin Schematic Namepin net-name | B2B -connectorConnector | indicatingIndicating |
|---|---|---|---|---|---|
| D1 | green | GLED | JM2-26 | available to user | |
| D2 | red | RLED | JM2-24 | available to user | |
| D3 | red | DONE | JM1-96 | FPGA-modul programmed properly |
Table 4: LED's functionality
Place
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Holders for
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Optional Pin-headers
The TEBB0714 base-board has place-holders with solder-pads to mount optional pin-headers capable to access the PL IO-bank pins of the mounted 4 x 5 SoM. With mounted pin-headers SoM's IO's are available to the user, a large quantity of these IO's are also usable as LVDS-pairs. This pin-headers provide also VCCIO voltages to operate the IO's properly.
Following table gives a summary of the optional pin-headers of the base-board:
Connector designatorDesignator | pinPin-header layoutLayout | # Count of IO's | # Count of LVDS-pairs | available VCCIOs | Available VCCIO's | Interfacesinterfaces |
|---|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 3 | 3.3V 3.3V_OUT (from mounted module) | - | |
| J17 | 2-row 50-pin | 42 (Bank 14) | 18 | 3.3V V_CFG (internal module's VCCIO: 3.3V or 1.8V, depending on configuration) | QSPI (6 IO's allocated) | |
| J20 | 2-row 50-pin | 42 (Bank 34) | 21 | 3.3V VCCIO34 (selectable: 1.8V, 2.5V, 3.3V_OUT) | - | |
| J3 | 2-row 16-pin | 12 | 2 | 3.3V V_CFG (internal module's VCCIO: 3.3V or 1.8V, depending on configuration) | JTAG (4 IO's allocated) UART (2 IO's allocated) ADC (1 LVDS-pair) Reference clock input MGT-CLK0 (1 LVDS-pair) |
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The external power-supply can be connected to the board by the following pins:
| Connector | 3.3V pin | GND pinPin |
|---|---|---|
| JX1 | JX1-5 | JX1-1, JX1-2 |
| J3 | J3-5 | J3-1, J3-2 |
| J4 | J4-5 | J4-1, J4-2 |
| J20 | J20-5, J20-46 | J20-1 , J20-2 , J20-49 , J20-50 |
| J17 | J17-5, J17-46 | J17-1 , J17-2 , J17-49 , J17-50 |
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Following table describes how to configure the base-board supply-voltage VCCIO34 by jumper J26:
baseBase-board supply-voltage Supply Voltage VCCIO34 | Jumper J26 |
|---|---|
| 1.8V | J26:1-2 |
| 2.5V | J26:3-4 |
| 3.3V | J26: 5-6 |
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ca. 25 g - Plain board
Document Change History
| dateDate | revisionRevision | authorsAuthors | descriptionDescription |
|---|---|---|---|
| 2017-02-20 | Ali Naseri | current TRM for TEBB0714-01 | |
| 2017-01-30 | 0.1 | Ali Naseri | Initial document |
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