Page History
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| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| 1.8V_EN / EN_1V8 | out | 106 | Power |
| 5V_EN | 115 | (currently controlled via S4-4) / currently_not_used | |
| C_TCK | 131 | JTAG J28 (XMOD2) / internal currently_not_used | |
| C_TDO | 137 | JTAG J28 (XMOD2) / internal currently_not_used | |
| C_TDO1 | 136 | JTAG J28 (XMOD2) / internal currently_not_used | |
| C_TMS | 130 | JTAG J28 (XMOD2) / internal currently_not_used | |
| CLK_A / AUD_CLK | out | 1 | AUDIO U3 CLK |
| CLK_CPLD / MEMS_CLKIN | in | 128 | U25 24,576MHz |
| DONE | in | 67 | PS Done / currently_not_used |
| EN_DDR | out | 86 | Enable DDR Power |
| EN_FMC / FMC_EN | out | 104 | FMC |
| EN_FPD | out | 81 | Enable PS FPD Power |
| EN_GT_L | out | 77 | Enable GT Power |
| EN_GT_R | out | 93 | Enable GT Power |
| EN_LPD | out | 84 | Enable PS LPL Power |
| EN_PL | out | 95 | Enable PL Power |
| EN_PLL_PWR | out | 78 | Enable SI5345 Power |
| EN_PSGT / EN_PSGTR | out | 75 | Enable PS GT Power |
| ERR_OUT / ERROR | in | 70 | PS Error Out / readable via RGIO / currently_not_used |
| ERR_STATUS / ERROR_STAT | in | 69 | PS Error Status / readable via RGIO / currently_not_used |
| F1PWM | out | 121 | FAN1 |
| F1SENSE | in | 125 | FAN1 |
| FAN_FMC_EN / FMC_FAN_EN | out | 132 | FMC FAN |
| FMC_PG_C2M | 141 | FMC / currently_not_used | |
| HD_LED_N / HDLED_N | out | 112 | J10 HD LED |
| HD_LED_P / HDLED_P | out | 110 | J10 HD LED |
| HDIO_SC0 / SC0 | in | 32 | FPGA IO / |
| HDIO_SC1 / SC1 | in | 33 | FPGA IO / forward to HD_LED_P / HDLED_P |
| HDIO_SC2 / SC2 | in | 34 | FPGA IO / currently_not_used |
| HDIO_SC3 / SC3 | out | 35 | FPGA IO / currently_not_used |
| HDIO_SC4 / SC4 | out | 25 | FPGA IO / currently_not_used |
| HDIO_SC5 / SC5 | out | 26 | FPGA IO / RGPIO |
| HDIO_SC6 / SC6 | in | 27 | FPGA IO / RGPIO CLK |
| HDIO_SC7 / SC7 | in | 28 | FPGA IO / RGPIO |
| I2C_SCL / SCL | in | 50 | I2C / currently_not_used |
| I2C_SDA / SCA | in | 52 | I2C / currently_not_used |
| INIT_B / INIT | in | 68 | PS init B / currently_not_used |
| JTAGENB | | 120 | external Pin for CPLD Firmware Update |
| LP_GOOD / PG_LPD | in | 83 | LP Power Good / currently_not_used |
| MIO24 | 38 | MIO / currently_not_used | |
| MIO25 | 39 | MIO / currently_not_used | |
| MIO30 | in | 48 | MIO / currently_not_usedforce reboot after FSBL-PLL config for PCIe |
| MIO31 | in | 49 | MIO / PCIe reset |
| MIO32 | 40 | MIO / currently_not_used | |
| MIO33 | 41 | MIO / currently_not_used | |
| MIO34 | 42 | MIO / currently_not_used | |
| MIO35 | 43 | MIO / currently_not_used | |
| MIO36 | 44 | MIO / currently_not_used | |
| MIO37 | 45 | MIO / currently_not_used | |
| MIO40 MIO40 | outin | 54 | MIO / forwarded to PWRLED_P / LED_P / SD_WP to FPGA |
| MIO41 | 55 | MIO / currently_not_used | |
| MIO42 | out | 60 | FPGA UART RX |
| MIO43 | in | 61 | FPGA UART TX |
| MIO44 | inout | 47 | MIO / forwarded to PWRLED_P / LED_P SD_WP to FPGA |
| MOD_EN | out | 119 | Module Power 3.3V Enable |
| MODE0 | out | 6 | Boot Mode |
| MODE1 | out | 9 | Boot Mode |
| MODE2 | out | 10 | Boot Mode |
| MODE3 | out | 11 | Boot Mode |
| MR / MRESETn | out | 92 | PS Reset |
| PCI_SFP_EN | out | 76 | SFP |
| PER_EN | out | 117 | Baseboard Power 3.3V Enable |
| PERST / PERSTn | out | 139 | PCIE Resetn |
| PG_DDR | in | 91 | Power Good / readable via RGIO / currently_not_used |
| PG_FPD | in | 85 | Power Good / readable via RGIO / currently_not_used |
| PG_GT_L | in | 96 | Power Good / readable via RGIO / currently_not_used |
| PG_GT_R | in | 94 | Power Good / readable via RGIO / currently_not_used |
| PG_PL | in | 82 | Power Good / readable via RGIO / currently_not_used |
| PG_PLL_1V8 / PG_PLL | in | 73 | Power Good / readable via RGIO / currently_not_used |
| PG_PSGT | in | 74 | Power Good / readable via RGIO / currently_not_used |
| PLL_LOLN / PLL_LOL | in | 58 | Module U5 Si5345 / readable via RGIO / currently_not_used |
| PLL_RST / PLL_RSTn | out | 56 | Module U5 Si5345 |
| PLL_SEL0 | out | 57 | Module U5 Si5345 |
| PLL_SEL1 | out | 59 | Module U5 Si5345 |
| POK_1V8 | 107 | Power / currently_not_used | |
| POK_FMC | in | 99 | FMC Power/ readable via RGIO / currently_not_used |
| PROG_B | inout | 71 | PS_PROG_B |
| PSON | out | 105 | ATX J20 PS_ON_N |
| PWR_BTN | in | 113 | Power Button S1 or J10 |
| PWRLED_N / LED_N | out | 111 | J10 PWR |
| PWRLED_P / LED_P | out | 109 | J10 PWR |
| PWROK | in | 100 | ATX J20 PWROK / readable via RGIO |
| RST_BTN | in | 114 | Reset Button S2 or J10 |
| S_1 | 127 | Beeper/ currently_not_used | |
| SC_IO0 / X0 | out | 12 | Master-Slave SC-Communication / Power Reset |
| SC_IO1 / X1 | out | 13 | Master-Slave SC-Communication / Power Reset |
| SC_IO2 / X2 | out | 14 | Master-Slave SC-Communication / currently_not_used |
| SC_IO3 / X3 | out | 20 | Master-Slave SC-Communication / currently_not_used |
| SC_IO4 / X4 | in | 21 | Master-Slave SC-Communication /MMC SD WP |
| SC_IO5 / X5 | in | 22 | Master-Slave SC-Communication / currently_not_used |
| SC_IO6 / X6 | in | 23 | Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable) |
| SC_IO7 / X7 | in | 24 | Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable) |
| SC_IO8 / dummy | 126 | / currently_not_used / ! not available on PCB REV2 ! | |
| SC2_SW1 | in | 133 | S5-1 / Boot Mode Selection / readable via RGIO |
| SC2_SW2 | in | 138 | S5-2 / Boot Mode Selection / readable via RGIO |
| SD_A_EN | out | 140 | Micro SD |
| SD_B_EN | out | 122 | MMC SD |
| SD_CD / SD_CD_OUT | out | 65 | SD Card detect to FPGA |
| SD_CD_B | in | 143 | MMC SD / readable via RGIO |
| SD_CD_S | in | 142 | Micro SD / readable via RGIO |
| SEL_SD / SD_SEL | out | 62 | Select SD |
| SRST_B / SRSTn | out | 19 | PS_SRST_B |
| STAT_LED2 / LED2 | out | 98 | LED D6 Green |
| STAT_LED3 / LED3 | out | 97 | LED D7 Red |
| XMOD2_A / XMOD_TXD | out | 5 | J12 (XMOD 1) |
| XMOD2_B / XMOD_RXD | in | 4 | J12 (XMOD 1) |
| XMOD2_E / XMOD_LED | out | 3 | J12 (XMOD 1) |
| XMOD2_G / XMOD_BTN | in | 2 | J12 (XMOD 1) / readable via RGIO |
...
Power Button is debounced.
Reset will be also set via modified FSBL, if PCIe is detected.
| Name | Description |
|---|---|
| PLL_RSTn | not RGPIO (0) when active else '1' |
| SRSTn | '1' |
| MRESETn | RST_BTN and PSON and "PS reboot via FSBL" |
| PERSTn | not RGPIO (1) and MIO31 when active else rst_btn_i and MIO31 |
| Master CPLD Reset | with PSON and Reset Button over CPLD interconnect. |
| PS reboot via FSBL | Reboot possible over FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button) |
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| Name | Description |
|---|---|
| LED2 D6 Green | RGPIO (5) when active else slow_blink when PSON is off else on |
| LED3 D7 Red | RGPIO (6) when active else not RST_BTN or mode_blink |
| LED_N | RGPIO (7) when active else off |
| LED_P | not RGPIO (8) when active else slow_blink when PSON is off else MIO44MIO40 |
| HDLED_N | RGPIO (9) when active else off |
| HDLED_P | not RGPIO (10) when active else SC0 |
| XMOD_LED Red | Done Pin: ON is not programmed, OFF programmed |
...
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV05 | REV02, REV03, REV04 |
| Revision 05 working in process | ||||||||||||||||||||||
| 2017-06-08 | v.23 | REV05 | REV02, REV03, REV04 | John Hartfiel | document style update | ||||||||||||||||||||||
| 2017-05-08 | v.22 | REV05 | REV02, REV03, REV04 | John Hartfiel | Revision 05 working in process | ||||||||||||||||||||||
| 2017-02-08 | v.19 | REV04 | REV02, REV03, REV04 | Revision 04 finished | |||||||||||||||||||||||
| 2016-04-11 | v.1 | --- |
| Initial release | |||||||||||||||||||||||
| All |
|
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