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 * TBD - To Be Determined soon with reference design setup.

Power Distribution Diagram

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Power-On Sequence

For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

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See also Xilinx datasheet DS187 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0720 module.

NOSEQ input signal

NOSEQ input signal from the carrier board can be used to control output of the two DC-DC converters U1 and U3. It works in conjunction with the System Controller CPLD firmware controlled ON_1V0 and ON_1V8 input signals of the U21 and U25 gate ICs.

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If NOSEQ input signal from the carrier board is low (logical 0), signals ON_1V0 and ON_1V8 can be driven by System Controller CPLD to control outputs of the U1 and U3 DC-DC converters.If NOSEQ input signal from the carrier board is high (logical 1), state of the ON_1V0 and ON_1V8 signals is irrelevant and DC-DC converters U1 and U3 outputs are always enabled.
Note

NB! Initial state of the ON_1V0 and ON_1V8 signals and therefore also functionality of the NOSEQ signal depend on the System Controller CPLD firmware.

Power Rails

B2B Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Note
VIN1, 3, 52, 4, 6, 8InputSupply voltage from baseboard.
3.3VIN13, 1591InputSupply voltage from baseboard. JM2-91 is VREF_JTAG.
VCCIO359, 11-InputHigh range bank voltage from baseboard.
VCCIO33-5InputHigh range bank voltage from baseboard.
VCCIO13-7, 9InputHigh range bank voltage from baseboard.
VCCIO34-1, 3InputHigh range bank voltage from baseboard.
VBAT_IN79-InputRTC battery-buffer supply voltage.
3.3V-10, 12OutputInternal 3.3V voltage level.
1.8V39-OutputInternal 1.8V voltage level.
1.5V 1)-19OutputInternal 1.5V voltage level.

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