Page History

...

LED	Color	Connected to	Description and Notes
D2	Green	LED1	Controlled by System Controller CPLD firmware.
D4	Green	DONE
D5	Red	LED2	Controlled by System Controller CPLD firmware.

...

PS-CLK

...

33.333333 MHz

...

U6

...

PS_CLK_500

...

PS subsystem main clock.

...

OTG-RCLK

...

52.000000 MHz

...

-

...

USB3320C reference clock.

...

MIO	Function	B2B Pin	Notes		MIO	Function	B2B Pin	Notes
0	GPIO	JM1-87	-		16..27	ETH0	-	RGMII

Page break

MIO	Function	B2B Pin	Notes	MIO	Function	B2B Pin	Notes
0	GPIO	JM1-87	-	16..27	ETH0	-	RGMII
1	QSPI0	-	SPI-CS	28..39	USB0	-	ULPI
2	QSPI0	-	SPI-DQ0	40	SD0	JM1-27	B2B
3	QSPI0	-	SPI-DQ1	41	SD0	JM1-25	B2B
4	QSPI0	-	SPI-DQ2	42	SD0	JM1-23	B2B
5	QSPI0	-	SPI-DQ3	43	SD0	JM1-21	B2B
6	QSPI0	-	SPI-SCK	44	SD0	JM1-19	B2B
7	GPIO	-	SC CPLD pin P11	45	SD0	JM1-17	B2B
8	-	-	3.3V	46	SD1	-	MMC-D0
9	-	JM1-91	B2B	47	SD1	-	MMC-CMD
10	-	JM1-95	B2B	48	SD1	-	MMC-CLK
11	-	JM1-93	B2B	49	SD1	-	MMC-D1
12	-	JM1-99	B2B	50	SD1	-	MMC-D2
13	-	JM1-97	B2B	51	SD1	-	MMC-D3
14	-	JM1-92	B2B	52	ETH0	-	MDC
15	-	JM1-85	B2B	53	ETH0	-	MDIO

...

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Clock Signal	Frequency	IC	FPGA	Notes
PS-CLK	33.333333 MHz	U6	PS_CLK_500	PS subsystem main clock.
OTG-RCLK	52.000000 MHz	U14	-	USB3320C reference clock.
ETH-CLK	25.000000 MHz	U9	-	88E1512 reference clock.

...

Versions Compared