Page History

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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8).  The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).

Ethernet PHY connection

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pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).

Ethernet PHY to B2B connections

USB Interface

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and reference clock input of the PHY is supplied from the on-board 52.000000 MHz oscillator (U14).

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On-board QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Clocking

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PS-CLK

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33.333333 MHz

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U6

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PS_CLK_500

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PS subsystem main clock.

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OTG-RCLK

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52.000000 MHz

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USB3320C reference clock.

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Processing System (PS) Peripherals

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MIO16..27

MIO52..53

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width and clock frequency used.

Clocking

Processing System (PS) Peripherals

¹⁾ Different make and model may be installed on different module variants.

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).

Ethernet PHY to FPGA/CPLD connections

RTC - Real Time Clock

Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I²C bus at slave address of 0x6F. General purpose RAM is at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

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A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48^TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.

On-board LEDs

Power and Power-On Sequence

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