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| Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Clocking
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PS-CLK
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33.333333 MHz
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U6
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PS_CLK_500
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PS subsystem main clock.
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OTG-RCLK
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52.000000 MHz
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-
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USB3320C reference clock.
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Processing System (PS) Peripherals
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MIO16..27
MIO52..53
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eMMC Flash Memory
eMMC NAND Flash (U15) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51 (see also Variants Currently in Production for options)1) Different make and model may be installed on different module variants.
Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).
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A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.
Clocking
| Clock Signal | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS-CLK | 33.333333 MHz | U6 | PS_CLK_500 | PS subsystem main clock. |
OTG-RCLK | 52.000000 MHz | U14 | - | USB3320C reference clock. |
| ETH-CLK | 25.000000 MHz | U9 | - | 88E1512 reference clock. |
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D2 | Green | LED1 | Controlled by System Controller CPLD firmware. |
| D4 | Green | DONE | |
| D5 | Red | LED2 | Controlled by System Controller CPLD firmware. |
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Overview
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