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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| RESIN | Input | Reset input | Active low reset input, default mapping forces POR_B reset to Zynq PS. |
| PGOOD | Output | Power good | Active high when all on-module power supplies are working properly. |
| MODE | Input | Boot mode | Force low for boot from the SD card. Latched at power-on only, not during soft reset! |
| EN1 | Input | Power enable | High enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high. |
| NOSEQ | Input | Power sequencing | Forces the 1.0V and 1.8V DC-DC converters always ON when high. |
| JTAGMODE | Input | JTAG select | Keep low for FPGA JTAG access. |
Default MIO Mapping
| MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes |
|---|---|---|---|---|---|---|---|
| 0 | GPIO | JM1-87 | - | 16..27 | ETH0 | - | RGMII |
| 1 | QSPI0 | - | SPI-CS | 28..39 | USB0 | - | OTG ULPI |
| 2 | QSPI0 | - | SPI-DQ0 | 40 | SD0 | JM1-27 | B2B |
| 3 | QSPI0 | - | SPI-DQ1 | 41 | SD0 | JM1-25 | B2B |
| 4 | QSPI0 | - | SPI-DQ2 | 42 | SD0 | JM1-23 | B2B |
| 5 | QSPI0 | - | SPI-DQ3 | 43 | SD0 | JM1-21 | B2B |
| 6 | QSPI0 | - | SPI-SCK | 44 | SD0 | JM1-19 | B2B |
| 7 | GPIO | - | SC CPLD pin P11 | 45 | SD0 | JM1-17 | B2B |
| 8 | - | - | 3.3V pull-up | 46 | SD1 | - | MMC-D0 |
| 9 | - | JM1-91 | B2B | 47 | SD1 | - | MMC-CMD |
| 10 | - | JM1-95 | B2B | 48 | SD1 | - | MMC-CLK |
| 11 | - | JM1-93 | B2B | 49 | SD1 | - | MMC-D1 |
| 12 | - | JM1-99 | B2B | 50 | SD1 | - | MMC-D2 |
| 13 | - | JM1-97 | B2B | 51 | SD1 | - | MMC-D3 |
| 14 | - | JM1-92 | B2B, SC CPLD pin M4 | 52 | ETH0 | - | ETH-MDC |
| 15 | - | JM1-85 | B2B, SC CPLD pin N4 | 53 | ETH0 | - | ETH-MDIO |
| 16 | ETH0 | ||||||
| 17 | ETH0 | ||||||
| 18 | ETH0 | ||||||
| 19 | ETH0 | ||||||
| 20 | ETH0 | ||||||
| 21 | ETH0 | ||||||
| 22 | ETH0 | ||||||
| 23 | ETH0 | ||||||
| 24 | ETH0 | ||||||
| 25 | ETH0 | ||||||
| 26 | ETH0 | ||||||
| 27 | ETH0 |
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Gigabit Ethernet
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Hi-speed USB ULPI PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
USB PHY connection
| USB PHY |
|---|
| Pin | SC CPLD Pin | B2B Name | Notes |
|---|
| REFSEL0..2 |
| - | - | Reference clock frequency select, all set to GND |
| = 52.000000 MHz. |
| RESETB |
| B14, bank 1 | - | Active low reset. |
| CLKOUT |
| - | - | ULPI output clock |
| connected to Zynq PS MIO36. |
| DP, DM |
| OTG-D_P, OTG-D_N | USB data lines. | |
| CPEN |
| VBUS_V_EN | External USB power switch active high enable signal. | |
| VBUS |
| - | USB-VBUS | Connect to USB VBUS via a series of resistors, see reference schematic. | |
| ID |
| - | OTG-ID | For A-device connect to the ground, for B-device leave floating. | |
| SPK_L |
| M5, bank 2 | - | In USB audio mode a switch connects the DM pin to the SPK_L |
| . |
| SPK_R |
| M8, bank 2 | - | In USB audio mode a switch connects the DP pin to the SPK_R |
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| . |
I2C Interface
On-board I2C devices are connected to the System Controller CPLD which acts as a I2C bus repeater for the Zynq SoC. System Controller CPLD signals X1, X3 and X7 are routed to Zynq SoC bank 34. Exact functionality depends on the System Controller CPLD firmware.
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| PHY Signal | Zynq PS Signal | SC CPLD Pin | PHY Signal | Zynq PS Signal | SC CPLD Pin | |
|---|---|---|---|---|---|---|
| ETH-MDC | MIO52 | L14 | ETH-TXD2 | MIO19 | - | |
| ETH-MDIO | MIO53 | K14 | ETH-TXD3 | MIO20 | - | |
| PHY_LED0 | - | F14 | ETH-TXCTL | MIO21 | - | |
| PHY_LED1 | - | D12 | ETH-RXCK | MIO22 | - | |
| PHY_LED2 | - | C13 | ETH-RXD0 | MIO23 | - | |
| PHY_CONFIG | - | C14 | ETH-RXD1 | MIO24 | - | |
| ETH-RST | - | E14 | ETH-RXD2 | MIO25 | - | |
| ETH-TXCK | MIO16 | - | ETH-RXD3 | MIO26 | - | |
| ETH-TXD0 | MIO17 | - | ETH-RXCTL | MIO27 | - | |
| ETH-TXD1 | MIO18 | - | CLK_125MHZ | - | G13 |
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High-speed USB ULPI PHY
Hi-speed USB ULPI PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
RTC - Real Time Clock
Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
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A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.
Clocking
| Clock Signal | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS-CLK | 33.333333 MHz | U6 | PS_CLK_500 | PS subsystem main clock. |
OTG-RCLK | 52.000000 MHz | U14 | - | USB3320C reference clock. |
| ETH-CLK | 25.000000 MHz | U9 | - | 88E1512 reference clock. |
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D2 | Green | LED1 | Controlled by System Controller CPLD firmware. |
| D4 | Green | DONE | |
| D5 | Red | LED2 | Controlled by System Controller CPLD firmware. |
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Overview
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