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Note
JTAGMODE pin 89 in B2B connector JM1 is used to select which device is accessible. Low - Xilinx Zynq, High - System Controller CPLD.

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System Controller I/O Pins

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Pin NameModeFunctionDefault Configuration
RESINInputReset inputActive low reset input, default mapping forces POR_B reset to Zynq PS.
PGOODOutputPower goodActive high when all on-module power supplies are working properly.
MODEInputBoot modeForce low for boot from the SD card. Latched at power-on only, not during soft reset!
EN1InputPower enableHigh enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high.
NOSEQInputPower sequencingForces the 1.0V and 1.8V DC-DC converters always ON when high.
JTAGMODEInputJTAG selectKeep low for FPGA JTAG access.

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Default MIO Mapping

MIOFunctionB2B PinNotesMIOFunctionB2B PinNotes
0GPIOJM1-87-27ETH0-ETH-RXCTL
1QSPI0-SPI-CS28USB0-OTG-DATA4
2QSPI0-SPI-DQ029USB0-OTG-DIR
3QSPI0-SPI-DQ130USB0-OTG-STP
4QSPI0-SPI-DQ231USB0-OTG-NXT
5QSPI0-SPI-DQ332USB0-OTG-DATA0
6QSPI0-SPI-SCK33USB0-OTG-DATA1
7GPIO-SC CPLD pin P1134USB0-OTG-DATA2
8--3.3V pull-up35USB0-OTG-DATA3
9-JM1-91B2B36USB0-OTG-CLK
10-JM1-95B2B37USB0-OTG-DATA5
11-JM1-93B2B38USB0-OTG-DATA6
12-JM1-99B2B39USB0-OTG-DATA7
13-JM1-97B2B40SD0JM1-27B2B, MIO40
14-JM1-92B2B, SC CPLD pin M441SD0JM1-25B2B, MIO41
15-JM1-85B2B, SC CPLD pin N442SD0JM1-23B2B, MIO42
16ETH0-ETH-TXCK43SD0JM1-21B2B, MIO43
17ETH0-ETH-TXD044SD0JM1-19B2B, MIO44
18ETH0-ETH-TXD145SD0JM1-17B2B, MIO45
19ETH0-ETH-TXD246SD1-MMC-D0
20ETH0-ETH-TXD347SD1-MMC-CMD
21ETH0-ETH-TXCTL48SD1-MMC-CLK
22ETH0-ETH-RXCK49SD1-MMC-D1
23ETH0-ETH-RXD050SD1-MMC-D2
24ETH0-ETH-RXD151SD1-MMC-D3
25ETH0-ETH-RXD252ETH0-ETH-MDC
26ETH0-ETH-RXD353ETH0-ETH-MDIO

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