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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| RESIN | Input | Reset input | Active low reset input, default mapping forces POR_B reset to Zynq PS. |
| PGOOD | Output | Power good | Active high when all on-module power supplies are working properly. |
| MODE | Input | Boot mode | Force low for boot from the SD card. Latched at power-on only, not during soft reset! |
| EN1 | Input | Power enable | High enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high. |
| NOSEQ | Input | Power sequencing | Forces the 1.0V and 1.8V DC-DC converters always ON when high. |
| JTAGMODE | Input | JTAG select | Keep low for FPGA JTAG access. |
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Default PS MIO Pin Mapping
| MIO | Function |
|---|
| Wired to | Notes | MIO | Function |
|---|
| Wired to | Notes |
|---|---|
| 0 |
| - | JM1-87 | - | 27 | ETH0 | U8-43 | ETH-RXCTL | |
|---|---|---|---|---|---|---|---|
| 1 | QSPI0 | U7-C2 | SPI-CS | 28 | USB0 | U18-7 | OTG-DATA4 |
| 2 | QSPI0 | U7-D3 | SPI-DQ0 | 29 | USB0 | U18-31 | OTG-DIR |
| 3 | QSPI0 | U7-D2 | SPI-DQ1 | 30 | USB0 | U18-29 | OTG-STP |
| 4 | QSPI0 | U7-C4 | SPI-DQ2 | 31 | USB0 | U18-2 | OTG-NXT |
| 5 | QSPI0 | U7-D4 | SPI-DQ3 | 32 | USB0 | U18-3 | OTG-DATA0 |
| 6 | QSPI0 | U7-B2 | SPI-SCK | 33 | USB0 | U18-4 | OTG-DATA1 |
| 7 | GPIO | U19-P11 | SC CPLD |
| 34 | USB0 | U18-5 | OTG-DATA2 | ||||
|---|---|---|---|---|---|---|---|
| 8 | - | - | 3.3V pull-up | 35 | USB0 | U18-6 | OTG-DATA3 |
| 9 | - | JM1-91 | B2B, MIO9 | 36 | USB0 | U18-1 | OTG-CLK |
| 10 | - | JM1-95 | B2B, MIO10 | 37 | USB0 | U18-9 | OTG-DATA5 |
| 11 | - | JM1-93 | B2B, MIO11 | 38 | USB0 | U18-10 | OTG-DATA6 |
| 12 | - | JM1-99 | B2B, MIO12 | 39 | USB0 | U18-13 | OTG-DATA7 |
| 13 | - | JM1-97 | B2B, MIO13 | 40 | SD0 | JM1-27 | B2B, MIO40 |
| 14 | - | JM1-92 U19-M4 | B2B, |
| U19-M4 | 41 | SD0 | JM1-25 | B2B, MIO41 |
|---|---|---|---|---|
| 15 | - | JM1-85 U19-N4 | B2B, |
| U19-N4 | 42 | SD0 | JM1-23 | B2B, MIO42 | |||
|---|---|---|---|---|---|---|---|
| 16 | ETH0 | U8-53 | ETH-TXCK | 43 | SD0 | JM1-21 | B2B, MIO43 |
| 17 | ETH0 | U8-50 | ETH-TXD0 | 44 | SD0 | JM1-19 | B2B, MIO44 |
| 18 | ETH0 | U8-51 | ETH-TXD1 | 45 | SD0 | JM1-17 | B2B, MIO45 |
| 19 | ETH0 | U8-54 | ETH-TXD2 | 46 | SD1 | U15-H3 | MMC-D0 |
| 20 | ETH0 | U8-55 | ETH-TXD3 | 47 | SD1 | U15-W5 | MMC-CMD |
| 21 | ETH0 | U8-56 | ETH-TXCTL | 48 | SD1 | U15-W6 | MMC-CLK |
| 22 | ETH0 | U8-46 | ETH-RXCK | 49 | SD1 | U15-H4 | MMC-D1 |
| 23 | ETH0 | U8-44 | ETH-RXD0 | 50 | SD1 | U15-H5 | MMC-D2 |
| 24 | ETH0 | U8-45 | ETH-RXD1 | 51 | SD1 | U15-J2 | MMC-D3 |
| 25 | ETH0 | U8-47 | ETH-RXD2 | 52 | ETH0 | U8-7 | ETH-MDC |
| 26 | ETH0 | U8-48 | ETH-RXD3 | 53 | ETH0 | U8-8 | ETH-MDIO |
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Gigabit Ethernet
NB! MIO0 to MIO15 are bank 500 MIOs and corresponding VCCO_MIO0_500 is 3.3V. MIO16 to MIO53 are bank 501 IOs and corresponding VCCO_MIO1_501 is 1.8V.
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Gigabit Ethernet
The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see section Default PS MIO Mapping.
SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).
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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).
Ethernet PHY to FPGA/SC CPLD connections
| PHY Signal | Zynq PS Signal | SC CPLD Pin | PHY Signal | Zynq PS Signal | SC CPLD Pin | ||
|---|---|---|---|---|---|---|---|
| ETH-MDC | MIO52 | L14 | ETH-TXD2 | MIO19 | - | ||
| ETH-MDIO | MIO53 | K14 | ETH-TXD3 | MIO20 | - | ||
| PHY_LED0 | - | F14 | ETH-TXCTL | MIO21 | - | ||
| PHY_LED1 | - | D12 | ETH-RXCK | MIO22 | - | ||
| PHY_LED2 | - | C13 | ETH-RXD0 | MIO23 | - | ||
| PHY_CONFIG | - | C14 | ETH-RXD1 | MIO24 | - | ||
| ETH-RST | - | E14 | ETH-RXD2 | MIO25 | - | ||
| ETH-TXCK | MIO16 | - | ETH-RXD3 | MIO26 | - | ||
| ETH-TXD0 | MIO17 | - | ETH-RXCTL | MIO27 | - | ||
| L14 | |||||||
| ETH-MDIO | K14 | ||||||
| PHY_LED0 | F14 | ||||||
| PHY_LED1 | D12 | ||||||
| PHY_LED2 | C13 | ||||||
| PHY_CONFIG | C14 | ||||||
| ETH-RST | E14 | ||||||
| CLK_125MHZ | ETH-TXD1 | MIO18 | - | CLK_125MHZ | - | G13 |
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High-speed USB ULPI PHY
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A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.
Clocking
| Source | Clock Signal | Frequency | ICDestination | FPGAPin Name | Notes |
|---|---|---|---|---|---|
| U6 | PS-CLK | 33.333333 MHz | U6U5 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U14 | OTG-RCLK | 52.000000 MHz | U14U18 | -REFCLK | USB3320C PHY reference clock. |
| U9 | ETH-CLK | 25.000000 MHz | U9U8- | XTAL_IN | 88E1512 PHY reference clock. |
On-board LEDs
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Overview
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