Page History

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• Xilinx XC7Z SoC (XC7Z020)
  - Processing System: Dual ARM Cortex-A9
       Unified 512 KByte L2 cache
       256 KByte on-chip memory
       54 multiplexed I/O pins (MIOs)
  - Programmable Logic: Artix-7 FPGA
       85 K logic cells
       560 KByte extensible block RAM (140x 36 Kbit BRAM blocks)
       220 programmable DSP slices
       Dual 12-bit 1Msps AD converter     200
• 54 multiplexed I/O pins (MIOs)
• 152 I/O pins (SelectIO interfaces)
• System Controller CPLD (Lattice LCMXO2-1200HC)
• 1 GByte DDR3/L memory, 2 x 256 Mbit x 16 (32-bit wide)
• 32 MByte Quad SPI Flash memory
• Gigabit Ethernet transceiver PHY (Marvell 88E1512)
• MAC address serial EEPROM with EUI-48™ node identity (11AA02E48)
• Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK)
• 3-axis accelerometer and 3-axis magnetometer (ST Microelectronics LSM303DTR) (Optional!)
• Real time clock with embedded crystal (Intersil ISL12020M): ±5ppm accuracy
• Atmel CryptoAuthentication element (Atmel ATSHA204A)
  
• Up to 32 GByte eMMC, usually 4 GByte, depends on module variant and assembly option
• User LED 1 (Green), user LED 2 (Red), user LED 3 - FPGA DONE (Green)
• 1.5A, PowerSoC DC-DC step-down converter (Enpirion EP53F8QI) for 1.8V power supply
• 1.5A, PowerSoC DC-DC step-down converter (Enpirion EP53F8QI) for 1.5V power supply
• 4A PowerSoC DC-DC step-down converter (Enpirion EN6347) for 1.0V power supply
• Trenz 4 x 5 module socket connector (3 x Samtec LSHM series connectors)

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Board to Board (B2B) I/Os

PL I/O signals connected to the signal connections between Zynq SoC's IO bank and B2B connector: I/O banks and B2B connectors, 152 total.

PS I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 14 total.

For detailed information about the pin-out, please refer to the Pin-out tables. 

JTAG Interface

JTAG access to the Xilinx Zynq and to the System Controller CPLD is provided through B2B connector JM2.

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