Page History
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| Bank | Type | Voltage | B2B | I/O Count | Notes |
|---|---|---|---|---|---|
| 13 | HR GPIO | VCCIO13 | JM2 | 48 | 24 LVDS pairs |
| 13 | HR GPIO | VCCIO13 | JM2 | 2 | B13_IO0 and B13_IO25 |
| 33 | HR GPIO | VCCIO33 | JM2 | 18 | 9 LVDS pairs |
| 34 | HR GPIO | VCCIO34 | JM3 | 36 | 18 LVDS pairs |
| 35 | HR GPIO | VCCIO35 | JM1 | 48 | 24 LVDS pairs |
PS I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 14 total.
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Hi-speed USB ULPI PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also Default PS MIO Pin Mapping). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
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On-board I2C devices are connected to the System Controller CPLD which acts as a I2C bus repeater for the Zynq SoC. System Controller CPLD signals X1, X3 and X7 are routed to Zynq SoC bank 34. Exact functionality depends on the System Controller CPLD firmware.
Zynq SoC to System Controller CPLD I2C bus
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