Page History
...
Hi-speed USB ULPI PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also Default PS MIO Pin Mapping). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
USB PHY connection
| USB PHY Pin | SC CPLD Pin | B2B Name | Notes |
|---|---|---|---|
| REFSEL0..2 | - | - | Reference clock frequency select, all set to GND = 52.000000 MHz. |
| RESETB | B14, bank 1 | - | Active low reset. |
| CLKOUT | - | - | ULPI output clock connected to Zynq PS MIO36. |
| DP, DM | OTG-D_P, OTG-D_N | USB data lines. | |
| CPEN | VBUS_V_EN | External USB power switch active high enable signal. | |
| VBUS | - | USB-VBUS | Connect to USB VBUS via a series of resistors, see reference schematic. |
| ID | - | OTG-ID | For A-device connect to the ground, for B-device leave floating. |
| SPK_L | M5, bank 2 | - | In USB audio mode a switch connects the DM pin to the SPK_L. |
| SPK_R | M8, bank 2 | - | In USB audio mode a switch connects the DP pin to the SPK_R. |
...
eMMC NAND Flash (U15) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51 (see also Variants Currently in Production for options). Depending on the module variant, different make and model of eMMC chips are available.
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).
...
Overview
Content Tools