Page History
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| Signal Name | SC CPLD Pin | SoC Pin | Notes |
|---|---|---|---|
| X1 | F1 | L16 | SCL, I2C clock. |
| X5 | J1 | P22 | SDA, I2C data out. |
| X7 | M1 | N22 | SDA, I2C data in. |
I2C devices slave device addresses
| I2C Device | I2C Address | IC | Notes |
|---|---|---|---|
| ISL12020M RTC | 0x6F | U20 | RTC registers. |
| ISL12020M SRAM | 0x57 | U20 | Battery backed RAM in RTC IC. |
| LSM303D | 0x1D | U22 | Optional, not soldered on current production variants. |
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MODE Signal State | Boot Mode |
|---|---|
High or open | SD Card |
Low or connected to the ground | QSPI |
On-board Peripherals
System Controller CPLD
Lattice Semiconductor MachXO2 (U19)
32 MByte Quad SPI Flash Memory
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The ATSHA204A Atmel CryptoAuthenticationTM chip (U10) is connected to the System Controller CPLD pin N14 via single-wire interface providing various security functions and features such as anti-counterfeiting, firmware/media protection, password validation, secure session key exchanging, secure data storage and more. Refer to the product datasheet for more information.
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Oscillators
| Source | Signal | Frequency | Destination | Pin Name | Notes |
|---|---|---|---|---|---|
| U6 | PS-CLK | 33.333333 MHz | U5 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U14 | OTG-RCLK | 52.000000 MHz | U18 | REFCLK | USB3320C PHY reference clock. |
| U9 | ETH-CLK | 25.000000 MHz | U8 | XTAL_IN | 88E1512 PHY reference clock. |
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Overview
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