Page History

...

PL I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 152 HR GPIOs total.

PS I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 14 total.

...

For detailed information about the pin-out, please refer to the Pin-out tables. 

JTAG Interface

JTAG access to the Zynq SoC and System Controller CPLD is provided through B2B connector JM2.

...

JTAG Signal

...

B2B Connector Pin

...

System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

...

MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.

For detailed information about the pin-out, please refer to the Pin-out tables. 

JTAG Interface

JTAG access to the Zynq SoC and System Controller CPLD is provided through B2B connector JM2.

System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Default PS MIO Pin Mapping

Default PS MIO Pin Mapping

• MIO0 to MIO15 are bank 500 MIOs with corresponding VCCO_MIO0_500 of 3.3V.
• MIO16 to MIO53 are bank 501 MIOs with corresponding VCCO_MIO1_501 of 1.8V.

  Page break

Ethernet Interface

The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see section Default PS MIO Pin Mapping.

SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).

Ethernet PHY to B2B connections

below).

Ethernet PHY to B2B connections

Ethernet PHY to Zynq SoC PS MIO ETH0 connections

USB Interface

Hi-speed USB ULPI PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also Default PS MIO Pin Mapping).

...