Page History
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| MIO | Function | Wired to | Notes | MIO | Function | Wired to | Notes | |
|---|---|---|---|---|---|---|---|---|
| 1 | QSPI0 | U7-C2 | SPI-CS | 28 | USB0 | U18-7 | OTG-DATA4 | |
| 2 | QSPI0 | U7-D3 | SPI-DQ0 | 29 | USB0 | U18-31 | OTG-DIR | |
| 3 | QSPI0 | U7-D2 | SPI-DQ1 | 30 | USB0 | U18-29 | OTG-STP | |
| 4 | QSPI0 | U7-C4 | SPI-DQ2 | 31 | USB0 | U18-2 | OTG-NXT | |
| 5 | QSPI0 | U7-D4 | SPI-DQ3 | 32 | USB0 | U18-3 | OTG-DATA0 | |
| 6 | QSPI0 | U7-B2 | SPI-SCK | 33 | USB0 | U18-4 | OTG-DATA1 | |
| 7 | GPIO | U19-P11 | SC CPLD | 34 | USB0 | U18-5 | OTG-DATA2 | |
| 8 | - | - | 3.3V pull-up | 35 | USB0 | U18-6 | OTG-DATA3 | |
| 36 | USB0 | U18-1 | OTG-CLK | |||||
| 37 | USB0 | U18-9 | OTG-DATA5 | |||||
| 38 | USB0 | U18-10 | OTG-DATA6 | |||||
| 39 | USB0 | U18-13 | OTG-DATA7 | |||||
| 40 | SD0 | JM1-27 | B2B, MIO40 | |||||
| 14 | - | JM1-92, U19-M4 | B2B, MIO14 | 41 | SD0 | JM1-25 | B2B, MIO41 | |
| 15 | - | JM1-85, U19-N4 | B2B, MIO15 | 42 | SD0 | JM1-23 | B2B, MIO42 | |
| 43 | SD0 | JM1-21 | B2B, MIO43 | |||||
| 44 | SD0 | JM1-19 | B2B, MIO44 | |||||
| 45 | SD0 | JM1-17 | B2B, MIO45 | |||||
| 46 | SD1 | U15-H3 | MMC-D0 | |||||
| 47 | SD1 | U15-W5 | MMC-CMD | |||||
| 48 | SD1 | U15-W6 | MMC-CLK | |||||
| 49 | SD1 | U15-H4 | MMC-D1 | |||||
| 50 | SD1 | U15-H5 | MMC-D2 | |||||
| 51 | SD1 | U15-J2 | MMC-D3 | |||||
| 52 | ETH0 | U8-7, U19-L14 | ETH-MDC | |||||
| 53 | ETH0 | U8-8, U19-K14 | ETH-MDIO |
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Ethernet Interface
Quad SPI Interface
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.
| MIO | Signal Name | U7 Pin |
|---|---|---|
| 1 | SPI-CS | C2 |
| 2 | SPI-DQ0/M0 | D3 |
| 3 | SPI-DQ1/M1 | D2 |
| 4 | SPI-DQ2/M2 | C4 |
| 5 | SPI-DQ3/M3 | D4 |
| 6 | SPI-SCK/M4 | B2 |
Ethernet Interface
The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see section Default PS MIO Pin Mapping.
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Hi-speed USB ULPI PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also Default PS MIO Pin Mapping).
USB PHY connection
| USB PHY Pin | SC CPLD Pin | B2B Name | Notes |
|---|---|---|---|
| REFSEL0..2 | - | - | Reference clock frequency select, all set to GND = 52.000000 MHz. |
| RESETB | B14, bank 1 | - | Active low reset. |
| CLKOUT | - | - | ULPI output clock connected to Zynq PS MIO36. |
| DP, DM | OTG-D_P, OTG-D_N | USB data lines. | |
| CPEN | VBUS_V_EN | External USB power switch active high enable signal. | |
| VBUS | - | USB-VBUS | Connect to USB VBUS via a series of resistors, see reference schematic. |
| ID | - | OTG-ID | For A-device connect to the ground, for B-device leave floating. |
| SPK_L | M5, bank 2 | - | In USB audio mode a switch connects the DM pin to the SPK_L. |
| SPK_R | M8, bank 2 | - | In USB audio mode a switch connects the DP pin to the SPK_R. |
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Overview
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