Page History
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Connector Designator | Pin-header Layout | Count of IO's | Count of LVDS-pairs | Available VCCIO's | Interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 3 | 3.3V 3.3V_OUT (from mounted module) | - |
| J17 | 2-row 50-pin | 42 (Bank 14) | 18 | 3.3V V_CFG (internal module's VCCIO: 3.3V or 1.8V, depending on configuration) | QSPI (6 IO's allocated) |
| J20 | 2-row 50-pin | 42 (Bank 34) | 21 | 3.3V VCCIO34 (selectable: 1.8V, 2.5V, 3.3V_OUT) | - |
| J3 | 2-row 16-pin | 12 | 2 | 3.3V V_CFG (internal module's VCCIO: 3.3V or 1.8V, depending on configuration) | JTAG (4 IO's) UART (2 IO's) ADC (1 LVDS-pair) Reference clock input MGT-CLK0 (1 LVDS-pair) |
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Overview
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