Page History
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| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| BOARD_STAT | out | 23 | STATUS to B2B |
| BOOT_MODE1 | in | 28 | Boot Mode Pin from B2B |
| BOOT_MODE2 | in | 27 | Boot Mode Pin from B2B |
| BOOT1 | out | 13 | Boot Mode Pin to FPGA (MIO4) |
| BOOT2 | out | 12 | Boot Mode Pin to FPGA (MIO5) |
| EN_3V3 | out | 25 | Enable 3.3V Switch |
| F_TCK | out | 8 | JTAG to FPGA |
| F_TDI | out | 9 | JTAG to FPGA |
| F_TDO | in | 11 | JTAG from FPGA |
| F_TMS | out | 10 | JTAG to FPGA |
| FPGA_IO | 5 | ||
| JTAGSEL | --- | 26 | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to FPGA, one: CPLD access) |
| nRST | in | 16 | Reset from B2B |
| nRST_IN | out | 4 | Manual Watchdog Reset (also available on B2B) |
| PS_POR_B | in | 14 | |
| TCK | in | 30 | JTAG from B2B |
| TDI | in | 32 | JTAG from B2B |
| TDO | out | 1 | JTAG to B2B |
| TMS | in | 29 | JTAG from B2B |
| WD_EN | in | 21 | Watchdog PL I/O |
| WD_HIT | in | 20 | Watchdog PL I/O |
| WDI | out | 17 | Watchdog trigger to external Watchdog IC |
Functional Description
JTAG
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Overview
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