Page History
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| MIO | Function | Wired to | Notes | MIO | Function | Wired to | Notes | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 28 | USB0 | U18-7 | GPIO | U19-P11 | SC CPLDOTG-DATA4 | ||||||||||
| 298 | USB0- | U18-31 | OTG-DIR3.3V pull-up | 30 | USB0 | U18-29 | OTG-STP | |||||||||
| 3140 | USB0SD0 | U18JM1-2 | OTG-NXT | 32 | USB0 | U18-3 | 27 | B2B, MIO40 | ||||||||
| 14 | - | JM1-92, U19-M4 | B2B, MIO14 | 41 | SD0 | JM1-25 | B2B, MIO41 | |||||||||
| 15 | - | JM1-85, U19-N4 | B2B, MIO15 | 42 | SD0 | JM1-23 | B2B, MIO42OTG-DATA0 | |||||||||
| 3343 | USB0SD0 | U18JM1-4 | OTG-DATA1 | |||||||||||||
| 7 | GPIO | U19-P11 | SC CPLD | 34 | USB0 | U18-5 | OTG-DATA2 | |||||||||
| 21 | B2B, MIO43 | |||||||||||||||
| 44 | SD0 | JM1-19 | B2B, MIO44 | |||||||||||||
| 45 | SD0 | JM1-17 | B2B, MIO45 | 8 | - | - | 3.3V pull-up | 35 | USB0 | U18-6 | OTG-DATA3 | |||||
| 3646 | USB0SD1 | U18U15-1H3 | OTGMMC-CLKD0 | |||||||||||||
| 3747 | USB0SD1 | U18U15-9W5 | OTGMMC-DATA5CMD | |||||||||||||
| 3848 | USB0SD1 | U18U15-10W6 | OTGMMC-DATA6CLK | |||||||||||||
| 3949 | USB0SD1 | U18U15-13H4 | OTGMMC-DATA7D1 | |||||||||||||
| 4050 | SD0SD1 | JM1U15-27 | B2B, MIO40 | |||||||||||||
| 14 | - | JM1-92, U19-M4 | B2B, MIO14 | 41 | SD0 | JM1-25 | B2B, MIO41 | |||||||||
| 15 | - | JM1-85, U19-N4 | B2B, MIO15 | 42 | SD0 | JM1-23 | B2B, MIO42 | |||||||||
| H5 | MMC-D2 | |||||||||||||||
| 51 | SD1 | U15-J2 | MMC-D3 | |||||||||||||
| 4352 | SD0ETH0 | JM1U8-21 | B2B, MIO43 | |||||||||||||
| 44 | SD0 | JM1-19 | B2B, MIO44 | |||||||||||||
| 7, U19-L14 | ETH-MDC | |||||||||||||||
| 4553 | SD0ETH0 | JM1U8-17 | B2B, MIO45 | |||||||||||||
| 46 | SD1 | U15-H3 | MMC-D0 | |||||||||||||
| 47 | SD1 | U15-W5 | MMC-CMD | |||||||||||||
| 48 | SD1 | U15-W6 | MMC-CLK | |||||||||||||
| 49 | SD1 | U15-H4 | MMC-D1 | |||||||||||||
| 50 | SD1 | U15-H5 | MMC-D2 | |||||||||||||
| 51 | SD1 | U15-J2 | MMC-D3 | |||||||||||||
| 52 | ETH0 | U8-7, U19-L14 | ETH-MDC | |||||||||||||
| 53 | ETH0 | U8-8, U19-K14 | ETH-MDIO |
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Quad SPI Interface
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.
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eMMC Interface
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Ethernet Interface
The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see tables below.
SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).
Ethernet PHY to B2B connections
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Ethernet PHY to Zynq SoC PS MIO ETH0 connections
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USB Interface
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| 8, U19-K14 | ETH-MDIO |
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Quad SPI Interface
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.
| MIO | Signal Name | U7 Pin |
|---|---|---|
| 1 | SPI-CS | C2 |
| 2 | SPI-DQ0/M0 | D3 |
| 3 | SPI-DQ1/M1 | D2 |
| 4 | SPI-DQ2/M2 | C4 |
| 5 | SPI-DQ3/M3 | D4 |
| 6 | SPI-SCK/M4 | B2 |
eMMC Interface
| MIO | Signal Name | U15 Pin |
|---|---|---|
| 46 | MMC-D0 | H3 |
| 47 | MMC-CMD | W5 |
| 48 | MMC-CLK | W6 |
| 49 | MMC-D1 | H4 |
| 50 | MMC-D2 | H5 |
| 51 | MMC-D3 | J2 |
Ethernet Interface
The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see tables below.
SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).
Ethernet PHY to B2B connections
| PHY Signal | B2B Pin | PHY Signal | B2B Pin | |
|---|---|---|---|---|
| SOUT_N | JM3-1 | PHY_MDI1_P | JM1-10 | |
| SOUT_P | JM3-3 | PHY_MDI1_N | JM1-12 | |
| SIN_N | JM3-2 | PHY_MDI2_P | JM1-16 | |
| SIN_P | JM3-4 | PHY_MDI2_N | JM1-18 | |
| PHY_MDI0_P | JM1-4 | PHY_MDI3_P | JM1-22 | |
| PHY_MDI0_N | JM1-6 | PHY_MDI3_N | JM1-24 |
Ethernet PHY to Zynq SoC PS MIO ETH0 connections
| PHY Signal | SoC MIO | PHY Signal | SoC MIO | |
|---|---|---|---|---|
| ETH-TXCK | 16 | ETH-RXCK | 22 | |
| ETH-TXD0 | 17 | ETH-RXD0 | 23 | |
| ETH-TXD1 | 18 | ETH-RXD1 | 24 | |
| ETH-TXD2 | 19 | ETH-RXD2 | 25 | |
| ETH-TXD3 | 20 | ETH-RXD3 | 26 | |
| ETH-TXCTL | 21 | ETH-RXCTL | 27 |
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USB Interface
Hi-speed USB ULPI PHY is provided by USB3320 from Microchip (U18). The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501.
| USB PHY Signal | Wired to | SoC MIO |
|---|---|---|
| OTG-DATA4 | U18-7 | 28 |
| OTG-DIR | U18-31 | 29 |
| OTG-STP | U18-29 | 30 |
| OTG-NXT | U18-2 | 31 |
| OTG-DATA0 | U18-3 | 32 |
| OTG-DATA1 | U18-4 | 33 |
| OTG-DATA2 | U18-5 | 34 |
| OTG-DATA3 | U18-6 | 35 |
| OTG-CLK | U18-1 | 36 |
| OTG-DATA5 | U18-9 | 37 |
| OTG-DATA6 | U18-10 | 38 |
| OTG-DATA7 | U18-13 | 39 |
USB PHY connection
| USB PHY Pin | SC CPLD Pin | B2B Name | Notes |
|---|---|---|---|
| REFSEL0..2 | - | - | Reference clock frequency select, all set to GND = 52.000000 MHz. |
| RESETB | B14, bank 1 | - | Active low reset. |
| CLKOUT | - | - | ULPI output clock connected to Zynq PS MIO36. |
| DP, DM | OTG-D_P, OTG-D_N | USB data lines. | |
| CPEN | VBUS_V_EN | External USB power switch active high enable signal. | |
| VBUS | - | USB-VBUS | Connect to USB VBUS via a series of resistors, see reference schematic. |
| ID | - | OTG-ID | For A-device connect to the ground, for B-device leave floating. |
| SPK_L | M5, bank 2 | - | In USB audio mode a switch connects the DM pin to the SPK_L. |
| SPK_R | M8, bank 2 | - | In USB audio mode a switch connects the DP pin to the SPK_R. |
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Overview
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