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Hi-speed USB ULPI PHY is provided by USB3320 from Microchip (U18). The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501.
| USB PHY Signal | Wired to | SoC MIO |
|---|---|---|
| OTG-DATA4 | U18-7 | 28 |
| OTG-DIR | U18-31 | 29 |
| OTG-STP | U18-29 | 30 |
| OTG-NXT | U18-2 | 31 |
| OTG-DATA0 | U18-3 | 32 |
| OTG-DATA1 | U18-4 | 33 |
| OTG-DATA2 | U18-5 | 34 |
| OTG-DATA3 | U18-6 | 35 |
| OTG-CLK | U18-1 | 36 |
| OTG-DATA5 | U18-9 | 37 |
| OTG-DATA6 | U18-10 | 38 |
| OTG-DATA7 | U18-13 | 39 |
USB PHY connection
| USB PHY Pin | SC CPLD Pin | B2B Name | Notes |
|---|---|---|---|
| REFSEL0..2 | - | - | Reference clock frequency select, all set to GND = 52.000000 MHz. |
| RESETB | B14, bank 1 | - | Active low reset. |
| CLKOUT | - | - | ULPI output clock connected to Zynq PS MIO36. |
| DP, DM | OTG-D_P, OTG-D_N | USB data lines. | |
| CPEN | VBUS_V_EN | External USB power switch active high enable signal. | |
| VBUS | - | USB-VBUS | Connect to USB VBUS via a series of resistors, see reference schematic. |
| ID | - | OTG-ID | For A-device connect to the ground, for B-device leave floating. |
| SPK_L | M5, bank 2 | - | In USB audio mode a switch connects the DM pin to the SPK_L. |
| SPK_R | M8, bank 2 | - | In USB audio mode a switch connects the DP pin to the SPK_R. |
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