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Table 1: Initial state of programmable devices on module on delivery.

Signals, Interfaces and Pins

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Table 2: General PL I/O to B2B connectors information.

PS MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.

MIO	B2B Pin	Bank	Voltage	Notes
0	JM1-87	500	3.3V
9	JM1-91	500	3.3V
10	JM1-95	500	3.3V
11	JM1-93	500	3.3V
12	JM1-99	500	3.3V
13	JM1-97	500	3.3V
14	JM1-92	500	3.3V
15	JM1-85	500	3.3V
40	JM1-27	501	1.8V	Zynq SoC SD0
41	JM1-25	501	1.8V	Zynq SoC SD0
42	JM1-23	501	1.8V	Zynq SoC SD0
43	JM1-21	501	1.8V	Zynq SoC SD0
44	JM1-19	501	1.8V	Zynq SoC SD0
45	JM1-17	501	1.8V	Zynq SoC SD0

Table 3: General PS MIO connections information.

For detailed information about the pin-out, please refer to the Pin-out tables.

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Table 4: JTAG pins connection.

Note
JTAGMODE pin 89 in B2B connector JM1 is used to switch access between devices, low selects Zynq SoC, high selects System Controller CPLD.

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Pin Name	Mode	Function	Default Configuration
RESIN	Input	Reset input	Active low reset input, default mapping forces POR_B reset to Zynq PS.
PGOOD	Output	Power good	Active high when all on-module power supplies are working properly.
MODE	Input	Boot mode	Force low for boot from the SD card. Latched at power-on only, not during soft reset!
EN1	Input	Power enable	High enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high.
NOSEQ	Input	Power sequencing	Forces the 1.0V and 1.8V DC-DC converters always ON when high.
JTAGMODE	Input	JTAG select	Keep low for FPGA JTAG access.

Table 5: System Controller CPLD special purpose pins description.

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53

MIO	Function	Wired to	NotesMIO	Function	Wired to	Notes
7	GPIO	U19-P11	SC CPLD
8	-	-	3.3V pull-up	52	ETH0	U8-7, U19-L14	ETH-MDC
14	-	JM1-92, U19-M4	B2B, MIO14		ETH0	U8-8, U19-K14	ETH-MDIO
15	-	JM1-85, U19-N4	B2B, MIO15

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PHY Signal	SoC MIO	PHY Signal	SoC MIO
ETH-TXCK	16	ETH-RXCK	22
ETH-TXD0	17	ETH-RXD0	23
ETH-TXD1	18	ETH-RXD1	24
ETH-TXD2	19	ETH-RXD2	25
ETH-TXD3	20	ETH-RXD3	26
ETH-TXCTL	21	ETH-RXCTL	27
ETH-MDC	52	ETH-MDIO	53

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Hi-speed USB ULPI PHY is provided by USB3320 from Microchip (U18). The ULPI interface is connected to the Zynq SoC PS USB0 via MIO28..39, bank 501.

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