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PS MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.
| MIO | B2B Pin | Bank | Voltage | Notes |
|---|---|---|---|---|
| 0 | JM1-87 | 500 | 3.3V | |
| 9 | JM1-91 | 500 | 3.3V | |
| 10 | JM1-95 | 500 | 3.3V | |
| 11 | JM1-93 | 500 | 3.3V | |
| 12 | JM1-99 | 500 | 3.3V | |
| 13 | JM1-97 | 500 | 3.3V | |
| 14 | JM1-92 | 500 | 3.3V |
| Also wired to U19-M4 | |||
| 15 | JM1-85 | 500 | 3.3V |
| Also wired to U19-N4 | ||||
| 40 | JM1-27 | 501 | 1.8V | Zynq SoC SD0 |
| 41 | JM1-25 | 501 | 1.8V | Zynq SoC SD0 |
| 42 | JM1-23 | 501 | 1.8V | Zynq SoC SD0 |
| 43 | JM1-21 | 501 | 1.8V | Zynq SoC SD0 |
| 44 | JM1-19 | 501 | 1.8V | Zynq SoC SD0 |
| 45 | JM1-17 | 501 | 1.8V | Zynq SoC SD0 |
Table 3: General PS MIO connections information.
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Special purpose pins are connected to System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| RESIN | Input | Reset input | Active low reset input, default mapping forces POR_B reset to Zynq PS. |
| PGOOD | Output | Power good | Active high when all on-module power supplies are working properly. |
| MODE | Input | Boot mode | Force low for boot from the SD card. Latched at power-on only, not during soft reset! |
| EN1 | Input | Power enable | High enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high. |
| NOSEQ | Input | Power sequencing | Forces the 1.0V and 1.8V DC-DC converters always ON when high. |
| JTAGMODE | Input | JTAG select | Keep low for FPGA JTAG access. |
| PS MIO7 | Input/Output | GPIO | Connected to System Controller CPLD pin P11, function depends on firmware |
Table 5: System Controller CPLD special purpose pins description.
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Default PS MIO Pin Mapping
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JM1-92, U19-M4
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JM1-85, U19-N4
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Quad SPI Interface
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