Page History
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On-board I2C devices are connected to the System Controller CPLD which acts as a I2C bus repeater for the Zynq SoC. System Controller CPLD signals X1, X3 and X7 are routed to Zynq SoC bank 34. Exact functionality depends on the System Controller CPLD firmware.
Zynq SoC to System Controller CPLD I2C bus
| Signal Name | SC CPLD Pin | SoC Pin | Notes |
|---|---|---|---|
| X1 | F1 | L16 | SCL, I2C clock. |
| X5 | J1 | P22 | SDA, I2C data out. |
| X7 | M1 | N22 | SDA, I2C data in. |
Table 12: Zynq SoC to System Controller CPLD I2C slave device addressesbus.
| I2C Device | I2C Address | IC | Notes |
|---|---|---|---|
| ISL12020M RTC | 0x6F | U20 | RTC registers. |
| ISL12020M SRAM | 0x57 | U20 | Battery backed RAM in RTC IC. |
| LSM303D | 0x1D | U22 | Optional, not soldered on current production variants. |
Table 13: I2C slave device addresses.
Boot Process
By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.
MODE Signal State | Boot Mode |
|---|---|
High or open | SD Card |
Low or connected to the ground | QSPI |
Table 14: Boot modes.
On-board Peripherals
System Controller CPLD
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| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
eMMC Flash Memory
eMMC NAND Flash memory device(U15) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51 (see also Variants Currently in Production for options). Depending on the module variant, different make and model of eMMC chips are available.
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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).Ethernet PHY to SC CPLD connections
| PHY Signal | SC CPLD Pin |
|---|---|
| ETH-MDC | L14 |
| ETH-MDIO | K14 |
| PHY_LED0 | F14 |
| PHY_LED1 | D12 |
| PHY_LED2 | C13 |
| PHY_CONFIG | C14 |
| ETH-RST | E14 |
| CLK_125MHZ | G13 |
Table 15: Ethernet PHY to SC CPLD connections.
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High-speed USB ULPI PHY
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| Source | Signal | Frequency | Destination | Pin Name | Notes |
|---|---|---|---|---|---|
| U6 | PS-CLK | 33.333333 MHz | U5 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U14 | OTG-RCLK | 52.000000 MHz | U18 | REFCLK | USB3320C PHY reference clock. |
| U9 | ETH-CLK | 25.000000 MHz | U8 | XTAL_IN | 88E1512 PHY reference clock. |
Table 16: Oscillators.
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D2 | Green | LED1 | Controlled by System Controller CPLD firmware. |
| D4 | Green | DONE | |
| D5 | Red | LED2 | Controlled by System Controller CPLD firmware. |
Table 17: On-board LEDs.
Power and Power-On Sequence
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| Power Input Pin | Typical Current |
|---|---|
| VIN | TBD* |
| 3.3VIN | TBD* |
Table 18: Power Consumption.
* TBD - To Be Determined soon with reference design setup.
Power Distribution Diagram
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Figure 3: Power distribution diagram.
| Note |
|---|
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
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Figure 4: Power sequencing.
| Note |
|---|
Initial state of the ON_1V0 and ON_1V8 signals and therefore also functionality of the NOSEQ signal depend on the System Controller CPLD firmware. |
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B2B Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Note |
|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from carrier board. |
| 3.3VIN | 13, 15 | 91 | Input | Supply voltage from carrier board. JM2-91 is VREF_JTAG. |
| VCCIO35 | 9, 11 | - | Input | High range bank voltage from carrier board. |
| VCCIO33 | - | 5 | Input | High range bank voltage from carrier board. |
| VCCIO13 | - | 7, 9 | Input | High range bank voltage from carrier board. |
| VCCIO34 | - | 1, 3 | Input | High range bank voltage from carrier board. |
| VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
| 1.8V | 39 | - | Output | Internal 1.8V voltage level. |
| 1.5V 1) | - | 19 | Output | Internal 1.5V voltage level. |
Table 19: Module power rails.
1) In case of module variant of TE0720-03-L1IF which uses Xilinx Zynq XC7Z020-L1CLG484I chip with lower power consumption, power rails named 1.5V and VCCO_DDR_502 voltage is actually 1.35V. To achieve this, a resistor with different value is used for R4 (see schematic of the TE0720-03-L1IF for more information).
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Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| 500 | 3.3V, VCCO_MIO0_500 | 3.3V | |
| 501 | 1.8V, VCCO_MIO1_501 | 1.8V | |
| 502 | 1.5V, VCCO_DDR_502 | 1.5V | |
| 0 Config | 3.3V | 3.3V | |
| 13 HR | VCCO13 | 1.2V to 3.3V | Supplied by the carrier board. |
| 33 HR | VCCIO33 | 1.2V to 3.3V | Supplied by the carrier board. |
| 34 HR | VCCIO34 | 1.2V to 3.3V | Supplied by the carrier board. |
| 35 HR | VCCIO35 | 1.2V to 3.3V | Supplied by the carrier board. |
Table 20: SoC bank voltages.
Board to Board Connectors
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| Module Variant | Zynq SoC | RAM | eMMC Size | Temperature Range | B2B Connector Height |
|---|---|---|---|---|---|
| TE0720-03-2IF | XC7Z020-2CLG484I | 1 GByte | 4 GByte | Industrial | 4.0 mm |
| TE0720-03-2IFC3 | XC7Z020-2CLG484I | 1 GByte | 4 GByte | Industrial | 2.5 mm |
| TE0720-03-2IFC8 | XC7Z020-2CLG484I | 1 GByte | 32 GByte | Industrial | 4.0 mm |
| TE0720-03-L1IF | XC7Z020-L1CLG484I | 512 MByte | 4 GByte | Industrial | 4.0 mm |
| TE0720-03-1CF | XC7Z020-1CLG484C | 1 GByte | 4 GByte | Commercial | 4.0 mm |
| TE0720-03-1CR | XC7Z020-1CLG484C | 256 MByte | - | Commercial | 4.0 mm |
| TE0720-03-14S-1C | XC7Z014S-1CLG484C | 1 GByte | 4 GByte | Commercial | 4.0 mm |
| TE0720-03-1QF | XA7Z020-1CLG484Q | 1 GByte | 4 GByte | Automotive | 4.0 mm |
Table 21: Module variants currently in production.
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 6.5 | V | EP53F8QI datasheet. |
| 3.3VIN supply voltage | -0.1 | 3.75 | V | TPS27082L and LCMXO2-1200HC datasheets. |
| Supply voltage for PS MIO banks | -0.5 | 3.6 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for MIO banks | -0.4 | VCCO_MIO + 0.55 | V | See Xilinx DS187 datasheet. (VCCO_MIO0_500, VCCO_MIO1_501) |
| Supply voltage for HR I/Os banks | -0.5 | 3.6 | V | See Xilinx DS187 datasheet. (VCCIO13, VCCIO33, VCCIO34, VCCIO35) |
| I/O input voltage for HR I/O banks | -0.4 | VCCIO + 0.55 | V | See Xilinx DS187 datasheet. |
Storage temperature | -40 | +85 | °C | - |
| Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed | -55 | +100 | °C | NB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C. |
Table 22: Module absolute and maximum ratings.
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
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| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 2.5 | 5.5 | V | EN6347QI and EP53F8QI datasheets. |
| 3.3VIN supply voltage | 3.135 | 3.465 | V | 3.3V +/- 5%. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.20 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
Table 23: Recommended operating conditions.
Operating Temperature Ranges
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Table 24: Hardware revision history.
There is no hardware revision number marking on the module.
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-07-31 | Jan Kumann | Initial document. |
Table 25: Document change history.
Disclaimer
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