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Figure 2: Main components of the module, description belowdescriptions follow.
- Xilinx Zynq XC7Z SoC, U5
- 4 Gbit DDR3/L SDRAM, U13
- 4 Gbit DDR3/L SDRAM, U12
- Low-power RTC with battery backed SRAM, U20
- 32 MByte Quad SPI Flash memory, U7
- Red LED (LED1), D5
- Green LED (LED2), D2
- System Controller CPLD, U19
- eMMC NAND Flash, U15
- 4A high-efficiency PowerSoC DC-DC step-down Converter (1V), U1
- Green LED (DONE), D4
- B2B connector Samtec Razor Beam™ LSHM-130, JM3
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- Hi-speed USB 2.0 ULPI transceiver, U18
- Gigabit Ethernet (GbE) transceiver, U8
- Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
- Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
- Low-dropout regulator (VBATT), U24
- DDR termination regulator, U4
- 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
- Atmel CryptoAuthentication chip, U10
- 2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
- Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
- 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
- 3A PFET load switch with configurable slew rate (3.3V), Q1
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Table 1: Initial state of programmable devices on delivery of the module.
Signals, Interfaces and Pins
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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| RESIN | Input | Reset input | Active low reset input, default mapping forces POR_B reset to Zynq PS. |
| PGOOD | Output | Power good | Active high when all on-module power supplies are working properly. |
| MODE | Input | Boot mode | Force low for boot from the SD card. Latched at power-on only, not during soft reset! |
| EN1 | Input | Power enable | High enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high. |
| NOSEQ | Input | Power sequencing | Forces the 1.0V and 1.8V DC-DC converters always ON when high. |
| JTAGMODE | Input | JTAG select | Keep low for FPGA JTAG access. |
| PS MIO7 | Input/Output | GPIO | Connected to System Controller CPLD pin P11, function depends on firmware |
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Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| 500 | 3.3V, VCCO_MIO0_500 | 3.3V | |
| 501 | 1.8V, VCCO_MIO1_501 | 1.8V | |
| 502 | 1.5V, VCCO_DDR_502 | 1.5V | |
| 0 Config | 3.3V | 3.3V | |
| 13 HR | VCCO13 | 1.2V to 3.3V | Supplied by the carrier board. |
| 33 HR | VCCIO33 | 1.2V to 3.3V | Supplied by the carrier board. |
| 34 HR | VCCIO34 | 1.2V to 3.3V | Supplied by the carrier board. |
| 35 HR | VCCIO35 | 1.2V to 3.3V | Supplied by the carrier board. |
Table 20: Zynq SoC bank voltages.
Board to Board Connectors
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Table 24: Hardware revision history table.
There is no hardware revision number marking on the module.
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-0708-3101 | Jan Kumann | Initial document. |
Table 25: Document change history table.
Disclaimer
| Include Page | ||||
|---|---|---|---|---|
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