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| Switch | Functionality |
|---|---|
| S3-1 | CM1: Mode pin 1 (routed to System Controller CPLD). |
| S3-2 | CM0: Mode pin 0 (routed to System Controller CPLD). |
| S3-3 | JTAGEN: Set to ON for normal JTAG operation. Has to be set to OFF position for System Controller CPLD JTAG access. |
| S3-4 | MIO0: Readable input signal by System Controller CPLD and mounted TE07xx modulePin from/to JB1-88 and PMOD (J1) connector. Direction depends on Module FPGA/SoC configuration. |
Table 1: DIP-switch S3 settings.
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On the TE0701 Carrier Board there are two push-buttons (S1 and S2) and are routed to the System Controller CPLD and available to the user. The default mapping of the push-buttons is as follows:
| Name | Default Mapping: |
|---|---|
| S1If S1 is pushed, the active-low RESet IN (RESIN) signal will be asserted. Note: This reset can also be forced by the FTDI USB to JTAG interface | Custom Button functionality CPLD Firmware dependent. |
| S2 | If S2 is pushed, the active-high Power ON (PON) signal (that is internally pulled-up) will be de-asserted, which can be considered as a "RESTART" function as all on-module power supplies will be switched off (except 3.3VIN) on button push and back on again on button release. The active-high PON signal is directly mapped to the active-high EN1 signal which is routed to the module's System Controller CPLD (e.g., on the TE0720) and directly used as a mandatory active-high enable signal to the power FET switch, enabling on-module 3.3V power supply output as well as all other DC-DC converters on the module. |
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There are two baseboard supply voltages VIOTA and VIOTB connected to the 4 x 5 SoM's PL IO-bank. The supply-voltages have following pin assignments on B2B-connectors:
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Table 4: Baseboard supply-voltages VIOTA and VIOTB
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| Date | Revision | Authors | Description |
|---|---|---|---|
| 2017-05-20 | John Hartfiel | Description correction. | |
| 2017-08-14 | v.52 | Jan Kumann | New physical dimensions drawing of the board. |
| 2017-05-16 | V51v.51 | Jan Kumann | A few overall improvements and corrections, new block diagram. |
| 2017-04-11 |
| Ali Naseri | added block diagram |
| 2017-02-15 | V45v.45 | Ali Naseri | added warning concerning the use of FTDI tools |
| 2017-02-15 | V40v.40 | Ali Naseri | added power-on sequence diagram |
| 2017-01-19 | V35v.35 | Ali Naseri | correction of table 3 (switch-positions to adjust FMC_VADJ) inserted hint to set and measure the PL IO-bank supply-voltages |
| 2017-01-13 | V20v.20 | Ali Naseri | added section for baseboard supply voltage configuration |
| 2016-11-29 | v.10V10
| Ali Naseri | TRM update due to new revision 06 of the carrier board. |
| 2016-11-28 | V4v.4 | Ali Naseri | TRM adjustment to the newest revision (05) of TE0701 Carrier Board. |
| 2014-02-18 | 0.2 | Sven-Ole Voigt | TE0701-03 (REV3) updated |
| 2014-01-05 | 0.1 | Sven-Ole Voigt | Initial release |
| All | Sven-Ole Voigt, Ali Naseri |
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