Page History

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Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

Boot Process

Trenz Electronic provides currently 2 Firmware variants, one for SD and one for QSPI usage. At the moment JTAG Mode is needed to write QSPI Flash with Xilinx Tools.

For more information read also TE0820 CPLD - BootMode section. 

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

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Check also TE0820 CPLD.

Default PS MIO Mapping

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On-board Peripherals

System Controller CPLD

Section currently not complete.

DDR4 Memory

Section currently not complete.

2 x 32 MByte Quad SPI Flash Memory

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Clocking

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

GTR Transceivers

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. There are also 3 clock sources for the transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Other two clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

On-board LEDs

There is one on-board red LED D1 wired to the PS DONE signal.

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

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*TBD - To be determined.

Power-on Sequence

For highest efficiency of on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

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1, 3, 5

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Table : Reference clock signals.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U21).

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U25) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

GTR Transceivers

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. There are also 3 clock sources for the transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Other two clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

On-board LEDs

There is one on-board red LED D1 wired to the PS DONE signal.

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

*TBD - To be determined.

Power Distribution Dependencies

Section currently not complete.

Power-On Sequence Diagram

For highest efficiency of on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Section currently not complete.

Power Rails

Bank Voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

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currently not in production, but for later usage:
TE0820-01-04CG-1E XCZU4CG-1SFVC784E 1 GByte DDR4 64 MByte Extended
TE0820-01-04EV-1E XCZU4EV-1SFVC784E 1 GByte DDR4 64 MByte Extended
  -->

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Bank Voltages

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See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

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Variants Currently In Production

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Module Variant

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SoC

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Technical Specifications

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Parameter	Min	Max	Units	Notes
VIN supply voltage

-0

2.

3

5

7

6.

0

6

V

See

EN6347QI and TPS82085SIL datasheets.

TPS82085S datasheet

3.3VIN supply voltage

-0

2.

1

375

3.

75

6

V

See LCMXO2-256HC

and TPS27082L

datasheet

.

PS I/O supply voltage, VCCO_PSIO

-0

1.

5

710

3.

630

465	V	Xilinx document DS925
PS I/O input voltage

-0

–0.

5

20	VCCO_PSIO + 0.

55

20	V	Xilinx document DS925
HP I/O

bank

banks supply voltage, VCCO

-0

1.

5

14

2

3.

0

465	V	Xilinx document DS925
HP I/O

bank

banks input voltage

-0.

55

20

VCCO + 0.

55

20	V	Xilinx document DS925
Voltage on module JTAG pins

-0

3.

4VCCO_0 + 0.55

V

VCCO_0 is 1.8V or 3.3V nominal. Xilinx document DS925

Storage temperature

-40

+85

°C

See eMMC datasheet.

Recommended Operating Conditions

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Operating Temperature Ranges

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm

• PCB thickness: 1.6 mm

• Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters. Additional sketches, drawings and schematics can be found here.

Image AddedImage Added

Weight

Revision History

Hardware Revision History

Hardware revision number is written on the PCB board next to the module model number separated by the dash.

 Image Added

Document Change History

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Table : Document change history

Operating Temperature Ranges

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm

• PCB thickness: 1.6 mm

• Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters. Additional sketches, drawings and schematics can be found here.

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Weight

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Boot Process

By default the TE-0820 supports SPI and SD Card boot modes which is controlled by MODE input signal from the B2B JM1 connector pin 32.

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MODE Signal State

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High or open

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SPI Flash

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Low or ground

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SD Card

Revision History

Hardware Revision History

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Notes

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Hardware revision number is written on the PCB board next to the module model number separated by the dash.

 Image Removed

Document Change History

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Date

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Revision

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Authors

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Description

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Disclaimer