Page History

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• Xilinx Zynq UltraScale+ MPSoC 784-pin package (ZU3EG, option for  ZU5EV)
  • Dual Cortex-A53 64-bit ARM v8 application processing unit (APU)
  • Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)

  • Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:

    • PCI Express® interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
  • 132 x HP PL I/Os (3 banks)
  • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
  • 4 x serial PS GTR transceivers
• 32-Bit DDR4, 4 GByte maximum
• Dual parallel SPI boot Flash, 512 MByte maximum
• 4 GByte eMMC (up to 64 GByte)
• GT reference clock input
• PLL for GT clocks (optional external reference)
• Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
• Hi-speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C)
• Programmable quad clock generator
• Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
• All power supplies on board
• Size: 50 x 40 mm

Block Diagram

Figure 1: TE020-02 block diagram.

Main Components

Figure 2: TE0820-02 main components.

1. Xilinx Zynq UltraScale+ ZU3EG MPSoC, U1
2. 4A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
3. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (PS_AVCC, 0.9V), U9
4. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (PS_AVTT, 1.8V), U13

5. 3A PFET load switch with configurable slew rate, fast transient isolation and hysteresis control (3.3V), Q1

6. Ultra-low supply-current voltage monitor with optional watchdog, U19
7. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
8. Low-power programmable oscillator @ 12.000000 MHz, U11
9. Miniature traceability S/N pad for low-cost, unique product identification
10. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (DDR_2V5, 2.5V), U4
11. 4 Gbit (256 x 16) DDR4 SDRAM, U3
12. 4 Gbit (256 x 16) DDR4 SDRAM, U2
13. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (DDR_1V2, 1.2V), U15
14. 1.8V, 256 Mbit multiple I/O serial flash memory, U17
15. 1.8V, 256 Mbit multiple I/O serial flash memory, U7
16. Low-power programmable oscillator @ 33.333333 MHz, U32
17. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (PS_VCCINT, 0.85V), U12
18. 350 mA, ultra-low VIN, RF low-dropout linear regulator with bias pin (PS_PLL, 1.2V), U23
19. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (1.8V), U20
20. B2B connector Samtec Razor Beam™ LSHM-150, JM2
21. DDR termination regulator with VTTREF buffered reference, U16
22. Low-power programmable oscillator @ 52.000000 MHz, U14
23. Highly integrated full featured hi-speed USB 2.0 ULPI   transceiver, U18
24. B2B connector Samtec Razor Beam™ LSHM-130, JM3
25.  I²C programmable, any  frequency , any output  quad clock generator, U10
26. B2B connector Samtec Razor Beam™ LSHM-150, JM1
27. Lattice Semiconductor MachXO2 System Controller CPLD, U21
28. 4 GByte eMMC memory, U6
    

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Table 1: Initial delivery state of programmable devices on the module.

Boot Process

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

Table 2: Boot mode pin description.

For more information refer to the TE0820 CPLD - BootMode section. 

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Table 3: General overview of board to board I/O signals.

For detailed information about the pin-out, please refer to the Pin-out table.

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Table 4: JTAG interface signals.

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

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Table 5: System Controller CPLD special purpose pins.

Check also TE0820 CPLD.

Default PS MIO Mapping

Table 6: TE0820-02 PS MIO mapping.

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

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Table 7: General overview of the Gigabit Ethernet PHY signals.

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 25.000000 MHz oscillator (U15).

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Table 8: General overview of the USB PHY signals.

I2C Interface

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C1 by default. I²C addresses for on-board devices are listed in the table below:

Table 9: Address table of the I²C bus slave devices.

On-On-board Peripherals

System Controller CPLD

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Table 10: General overview of the on-board quad clock generator I/O signals.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 11: Reference clock signals.

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Table 12: Power consumption.

*TBD - To be determined.

Power Distribution Dependencies

Section currently not complete.

Power-On Sequence Diagram

Module has two power input rails which can be connected to the single power source.

Image Added

Figure 3: TE0820-02 power distribution diagram.

Power-On Sequence Diagram

For highest efficiency of on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

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Table 13: Te0820-02 power rails.

Bank Voltages

Table 14: TE0820-02 I/O bank voltages.

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

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Table 15: TE0820-02 variants.

<!--
currently not in production, but for later usage:
TE0820-02-04CG-1E XCZU4CG-1SFVC784E 1 GByte DDR4 64 MByte Extended
TE0820-02-04EV-1E XCZU4EV-1SFVC784E 1 GByte DDR4 64 MByte Extended
  -->

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Table 16: Module absolute maximum ratings.

Recommended Operating Conditions

Table 17: Recommended operating conditions.

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All dimensions are shown in millimeters. Additional sketches, drawings and schematics can be found here.

Weight

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Figure 4: TE0820 module physical dimensions.

Revision History

Hardware Revision History

Table 18: Hardware revision history table.

Hardware revision number is written on the PCB board next to the module model number separated by the dash.

Image Added

Figure 5: TE0820 module hardware revision.  Image Removed

Document Change History

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Table 19: Document change history.

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