Page History
...
Table 5: System Controller CPLD special purpose pins.
See also TE0820 CPLD.
| Page break |
|---|
Default PS MIO Mapping
| PS MIO | Function | B2B Pin | Connected to | PS MIO | Function | B2B Pin | Connected to | |
|---|---|---|---|---|---|---|---|---|
| 0 | SPI0 | - | U7-B2, CLK | 40..45 | - | - | Not connected | |
| 1 | SPI0 | - | U7-D2, DO/IO1 | 46 | SD | JM1-17 | B2B, SD_DAT3 | |
| 2 | SPI0 | - | U7-C4, WP/IO2 | 47 | SD | JM1-19 | B2B, SD_DAT2 | |
| 3 | SPI0 | - | U7-D4, HOLD/IO3 | 48 | SD | JM1-21 | B2B, SD_DAT1 | |
| 4 | SPI0 | - | U7-D3, DI/IO0 | 49 | SD | JM1-23 | B2B, SD_DAT0 | |
| 5 | SPI0 | - | U7-C2, CS | 50 | SD | JM1-25 | B2B, SD_CMD | |
| 6 | N/A | - | Not connected | 51 | SD | JM1-27 | B2B, SD_CLK | |
| 7 | SPI1 | - | U17-C2, CS | 52 | USB_PHY | - | U18-31, OTG-DIR | |
| 8 | SPI1 | - | U17-D3, DI/IO0 | 53 | USB_PHY | - | U18-31, OTG-DIR | |
| 9 | SPI1 | - | U17-D2, DO/IO1 | 54 | USB_PHY | - | U18-5, OTG-DATA2 | |
| 10 | SPI1 | - | U17-C4, WP/IO2 | 55 | USB_PHY | - | U18-2, OTG-NXT | |
| 11 | SPI1 | - | U17-D4, HOLD/IO3 | 56 | USB_PHY | - | U18-3, OTG-DATA0 | |
| 12 | SPI1 | - | U17-B2, CLK | 57 | USB_PHY | - | U18-4, OTG-DATA1 | |
| 13..20 | eMMC | - | U6, MMC-D0..D7 | 58 | USB_PHY | - | U18-29, OTG-STP | |
| 21 | eMMC | - | U6, MMC-CMD | 59 | USB_PHY | - | U18-6, OTG-DATA3 | |
| 22 | eMMC | - | U6, MMC-CLKR | 60 | USB_PHY | - | U18-7, OTG-DATA4 | |
| 23 | eMMC | - | U6, MMC-RST | 61 | USB_PHY | - | U18-9, OTG-DATA5 | |
| 24 | ETH | - | U8, ETH-RST | 62 | USB_PHY | - | U18-10, OTG-DATA6 | |
| 25 | USB_PHY | - | U18, OTG-RST | 63 | USB_PHY | - | U18-13, OTG-DATA7 | |
| 26 | MIO | JM1-95 | B2B | 64 | ETH | - | U8-53, ETH-TXCK | |
| 27 | MIO | JM1-93 | B2B | 65..66 | ETH | - | U8-50..51, ETH-TXD0..1 | |
| 28 | MIO | JM1-99 | B2B | 67..68 | ETH | - | U8-54..55, ETH-TXD2..3 | |
| 29 | MIO | JM1-99 | B2B | 69 | ETH | - | U8-56, ETH-TXCTL | |
| 30 | MIO | JM1-92 | B2B | 70 | ETH | - | U8-46, ETH-RXCK | |
| 31 | MIO | JM1-85 | B2B (UART RX) | 71..72 | ETH | - | U8-44..45, ETH-RXD0..1 | |
| 32 | MIO | JM1-91 | B2B (UART TX) | 73..74 | ETH | - | U8-47..48, ETH-RXD2..3 | |
| 33 | MIO | JM1-87 | B2B | 75 | ETH | - | U8-43, ETH-RXCTL | |
| 34..37 | N/A | - | Not connected | 76 | ETH | - | U8-7, ETH-MDC | |
| 38 | I2C | - | U10-12, SCL | 77 | ETH | - | U8-8, ETH-MDIO | |
| 39 | I2C | - | U10-19, SDA |
Table 6: TE0820-02 PS MIO mapping.
| Page break |
|---|
Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.
...
Overview
Content Tools