Page History
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2 Firmware variants with swapped external reset input and output available.
Figure1: Firmware for TEB0729 without modification,
|  Figure2: Firmware for TEB0729 with modification,
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Feature Summary
- Boot Mode
- JTAG connection
- Power Management
- Watchdog Management
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Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGSEL (logical one for CPLD, logical zero for FPGA) on J2-111.
Power
3.3V (EN_3V3) is enabled.
Boot Mode
Boot Mode Pins routed through the CPLD. MIO2 and MIO3 are connected to GND via resistor.
| Pin | FPGA IO | Value | |||
|---|---|---|---|---|---|
| BOOT1 (BMODE1) | MIO4 | 0 | 1 | 0 | 1 |
| BOOT2 (BMODE2) | MIO5 | 0 | 0 | 1 | 1 |
| Boot Modus | JTAG | not supported | QSPI | SD |
Appx. A: Change History and Legal Notices
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Overview
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