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Boot Mode Pins routed through the CPLD. MIO2 and MIO3 are connected to GND via resistor.
| Pin | FPGA IO |
|---|---|
| BOOT_MODE1 (BOOT1 (BMODE1) | MIO4 |
| BOOT_MODE2 (BOOT2 (BMODE2) | MIO5 |
| BOOT1 | BOOT2 | Boot Mode |
|---|---|---|
| 0 | 0 | JTAG |
| 0 | 1 | QSPI |
| 1 | 0 | not supported |
| 1 | 1 | SD |
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2 Variant available,depends on carrier board connection, see Figure 1 and 2. The swapped signals and nRST_IN pulse limitation on variant 1 are the only difference between this two variants.
Variant 1 (Figure 1, SC729_rev02org.jed):
| IOs | B2B | Direction | Description |
|---|---|---|---|
| nRST | J2-89 | in | Main Reset to module |
| nRST_IN | J2-91 | out | Main reset to carrier and PS_POR_B for approx. 1,9 us. |
Variant 2 (Figure 2, SC729_rev02plus.jed):
| IOs | B2B | Direction | Description |
|---|---|---|---|
| nRST | J2-89 | out | Main reset to carrier and PS_POR_B |
| nRST_IN | J2-91 | in | Main Reset to module |
1V Power supply:
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