Page History

...

The I/O signals are routed from the FPGA I/O banks to the FMC connector as LVDS pairs:

Bank	I/O Signal count	LVDS pairs count	VCCO bank Voltage	Notes
Bank 19	92	46	1.8V	-
Bank 39	42	21	VIO_B_FMC	Bank voltage VIO_B_FMC must be supplied by FMC connector pins J2-J39, J2-K40 Bank's VREF pin (VREF_B_M2C) available on FMC connector pin J2-K1 (external reference voltage)
Bank 37	34	17	1.8V	Bank's VREF pin (VREF_A_M2C) available on FMC connector pin J2-H1 (external reference voltage)
Bank 38	34	17	1.8V	Bank's VREF pin (VREF_A_M2C) available on FMC connector pin J2-H1 (external reference voltage)

Table 2: FMC connector pin-outs of available logic banks of the FPGA.

...

The MGT banks have also clock input-pins which are exposed to the FMC connector. Following MGT lanes are available on the FMC connector:

Bank

I/O signal count

LVDS pairs count

MGT lanes count

bank's reference clock (LVDS pair)

116

10

5

2

1 clock-signal from clock synthesizer U9 to bank's pins T6/T5

117

20

10

4

2 clock-signals from clock FMC connector GBTCLK0_M2C and GBTCLK1_M2C (pins J2-D4/J2-D5 and J2-B20/J2-B21) to bank's pins M6/M5 and P6/P5

118

20

10

4

1 reference clock from clock synthesizer U9 to bank's pins F6/F5

1 reference clock from programmable quad PLL clock generator U13 to bank's pins H6/H5

Table 3: FMC connector pin-outs of available MGT lanes of the FPGA.

...

The FMC connector provides further interfaces like ' JTAG ' and ' I²C ' interfaces to the System Controller CPLD:

...

Versions Compared