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Table 13: I/O pin description of PLL clock generator Si5338A.
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Ultra low-noise high-performance clock synthesizer
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The on-board voltages of the TEC0330 FPGA board will be powered - up in order of a determined sequence after the external voltages ' 12V ' on connector J5 and ' 3V3PCI ' on connector J1 are available.
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
Following diagram clarifies describes the sequence of enabling the particular on-board voltages:
Figure 3: FPGA board TEC0330-03 Power-On sequence diagram.
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