Page History

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For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Lane	Bank	Type	Signal Name	B2B Pin	FPGA Pin
0	505	GTR	B505_RX0_P B505_RX0_N B505_TX0_P B505_TX0_N	JM3-26 JM3-28 JM3-25 JM3-27	PS_MGTRRXP0_505, F27 PS_MGTRRXN0_505, F28 PS_MGTRTXP0_505, E25 PS_MGTRTXN0_505, E26
1	505	GTR	B505_RX1_P B505_RX1_N B505_TX1_P B505_TX1_N	JM3-20 JM3-22 JM3-19 JM3-21	PS_MGTRRXP1_505, D27 PS_MGTRRXN1_505, D28 PS_MGTRTXP1_505, D23 PS_MGTRTXN1_505, D24
2	505	GTR	B505_RX2_P B505_RX2_N B505_TX2_P B505_TX2_N	JM3-14 JM3-16 JM3-13 JM3-15	PS_MGTRRXP0_505, B27 PS_MGTRRXN0_505, B28 PS_MGTRTXP0_505, C25 PS_MGTRTXN0_505, C26
3	505	GTR	B505_RX3_P B505_RX3_N B505_TX3_P B505_TX3_N	JM3-8 JM3-10 JM3-7 JM3-9	PS_MGTRRXP1_505, A25 PS_MGTRRXN1_505, A26 PS_MGTRTXP1_505, B23 PS_MGTRTXN1_505, B24

Table 4: MGT lanes.

Below are listed MGT banks reference clock sources.

Clock signal	Bank	Source	FPGA Pin	Notes
B505_CLK0_P	505	B2B, JM3-31	PS_MGTREFCLK0P_505,	Supplied by the carrier board.
B505_CLK0_N	505	B2B, JM3-33	PS_MGTREFCLK0N_505,	Supplied by the carrier board.
B505_CLK1_P	505	U10, CLK2A	PS_MGTREFCLK1P_505,	On-board Si5338A.
B505_CLK1_N	505	U10, CLK2B	PS_MGTREFCLK1N_505,	On-board Si5338A.
B505_CLK2_P	505	N/A	PS_MGTREFCLK2P_505,	Not connected.
B505_CLK2_N	505	N/A	PS_MGTREFCLK2N_505,	Not connected.
B505_CLK3_P	505	U10, CLK1A	PS_MGTREFCLK3P_505,	On-board Si5338A.
B505_CLK3_N	505	U10, CLK1B	PS_MGTREFCLK3N_505,	On-board Si5338A.

Table 5: MGT reference clock sources.

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

JTAG Signal	B2B Connector Pin
TMS	JM2-93
TDI	JM2-95
TDO	JM2-97
TCK	JM2-99

Table 46: JTAG interface signals.

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

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Pin Name	Mode	Function	Default Configuration
EN1	Input	Power Enable	No hard wired function on PCB. When forced low, pulls up PGOOD, goes low without effect on power management.
PGOOD	Output	Power Good	Active high when all on-module power supplies are working properly.
NOSEQ	-	-	No function.
RESIN	Input	Reset	Active low reset, gated to POR_B.
JTAGEN	Input	JTAG Select	Low for normal operation, high for CPLD JTAG access.

Table 57: System Controller CPLD special purpose pins.

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PS MIO	Function	B2B Pin	Connected to	PS MIO	Function	B2B Pin	Connected to
0	SPI0	-	U7-B2, CLK	40..45	-	-	Not connected
1	SPI0	-	U7-D2, DO/IO1	46	SD	JM1-17	B2B, SD_DAT3
2	SPI0	-	U7-C4, WP/IO2	47	SD	JM1-19	B2B, SD_DAT2
3	SPI0	-	U7-D4, HOLD/IO3	48	SD	JM1-21	B2B, SD_DAT1
4	SPI0	-	U7-D3, DI/IO0	49	SD	JM1-23	B2B, SD_DAT0
5	SPI0	-	U7-C2, CS	50	SD	JM1-25	B2B, SD_CMD
6	N/A	-	Not connected	51	SD	JM1-27	B2B, SD_CLK
7	SPI1	-	U17-C2, CS	52	USB_PHY	-	U18-31, OTG-DIR
8	SPI1	-	U17-D3, DI/IO0	53	USB_PHY	-	U18-31, OTG-DIR
9	SPI1	-	U17-D2, DO/IO1	54	USB_PHY	-	U18-5, OTG-DATA2
10	SPI1	-	U17-C4, WP/IO2	55	USB_PHY	-	U18-2, OTG-NXT
11	SPI1	-	U17-D4, HOLD/IO3	56	USB_PHY	-	U18-3, OTG-DATA0
12	SPI1	-	U17-B2, CLK	57	USB_PHY	-	U18-4, OTG-DATA1
13..20	eMMC	-	U6, MMC-D0..D7	58	USB_PHY	-	U18-29, OTG-STP
21	eMMC	-	U6, MMC-CMD	59	USB_PHY	-	U18-6, OTG-DATA3
22	eMMC	-	U6, MMC-CLKR	60	USB_PHY	-	U18-7, OTG-DATA4
23	eMMC	-	U6, MMC-RST	61	USB_PHY	-	U18-9, OTG-DATA5
24	ETH	-	U8, ETH-RST	62	USB_PHY	-	U18-10, OTG-DATA6
25	USB_PHY	-	U18, OTG-RST	63	USB_PHY	-	U18-13, OTG-DATA7
26	MIO	JM1-95	B2B	64	ETH	-	U8-53, ETH-TXCK
27	MIO	JM1-93	B2B	65..66	ETH	-	U8-50..51, ETH-TXD0..1
28	MIO	JM1-99	B2B	67..68	ETH	-	U8-54..55, ETH-TXD2..3
29	MIO	JM1-99	B2B	69	ETH	-	U8-56, ETH-TXCTL
30	MIO	JM1-92	B2B	70	ETH	-	U8-46, ETH-RXCK
31	MIO	JM1-85	B2B (UART RX)	71..72	ETH	-	U8-44..45, ETH-RXD0..1
32	MIO	JM1-91	B2B (UART TX)	73..74	ETH	-	U8-47..48, ETH-RXD2..3
33	MIO	JM1-87	B2B	75	ETH	-	U8-43, ETH-RXCTL
38	I²C	-	U10-12, SCL	76	ETH	-	U8-7, ETH-MDC
39	I²C	-	U10-19, SDA	77	ETH	-	U8-8, ETH-MDIO

Table 68: TE0820-02 PS MIO mapping.

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PHY Pin	ZYNQ PS	ZYNQ PL	Notes
MDC/MDIO	MIO76, MIO77	-	-
LED0	-	K8	Can be routed via PL to any free PL I/O pin in B2B connector.
LED1	-	-	CPLD pin 17.
LED2	-	-	Not connected.
CONFIG	-	-	Wired to the 1.8V.
RESETn	MIO24	-	-
RGMII	MIO64..MIO75	-	-
SGMII	-	-	Routed to the B2B connector JM3.

Table 79: General overview of the Gigabit Ethernet PHY signals.

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PHY Pin	ZYNQ Pin	B2B Name	Notes
ULPI	MIO52..63	-	Zynq USB0 MIO pins are connected to the USB PHY.
REFCLK	-	-	52.000000 MHz from on-board oscillator (U14).
REFSEL[0..2]	-	-	Reference clock frequency select, all set to GND selects 52.000000 MHz.
RESETB	MIO25	-	Active low reset.
CLKOUT	MIO52	-	Connected to 1.8V, selects reference clock operation mode.
DP, DM	-	OTG_D_P, OTG_D_N	USB data lines routed to B2B connector JM3 pins 47 and 49.
CPEN	-	VBUS_V_EN	External USB power switch active high enable signal, routed to JM3 pin 17.
VBUS	-	USB_VBUS	Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
ID	-	OTG_ID	For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

Table 810: General overview of the USB PHY signals.

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I2C Device	I2C Address	Notes
Si5338A PLL	0x70	-
EEPROM	0x53	-

Table 911: Address table of the I²C bus slave devices.

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Signal	Frequency	Notes
IN1/IN2	-	Not used (external clock signal supply).
IN3	25.000000 MHz	Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U11).
IN4	-	LSB of the default I²C address, wired to ground mean address is 0x70.
IN5	-	Not connected.
IN6	-	Wired to ground.
CLK0 A/B	-	Bank 65 clock input, pins K9 and J9.
CLK1 A/B	-	MGT reference clock 3 to FPGA Bank 505 MGT.
CLK2 A/B	-	MGT reference clock 1 to FPGA Bank 505 MGT.
CLK3 A/B	-	Not connected.

Table 1012: General overview of the on-board quad clock generator I/O signals.

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Clock Source	Schematic Name	Frequency	Clock Destination
SiTime SiT8008BI oscillator, U21	PS_CLK	33.333333 MHz	Zynq MPSoC U1,pin R16
SiTime SiT8008BI oscillator, U21	-	25.000000 MHz	Quad PLL clock generator U10, pin 3, and Ethernet PHY U8, pin 34

Table 1113: Reference clock signals.

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Power Input	Typical Current
VIN	TBD*
3.3VIN	TBD*

Table 1214: Power consumption.

*TBD - To be determined.

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Power Rail Name on B2B Connector	JM1 Pins	JM2 Pins	Direction	Notes
VIN	1, 3, 5	2, 4, 6, 8	Input	Supply voltage from the carrier board.
3.3V	-	10, 12	Output	Internal 3.3V voltage level.
3.3VIN	13, 15, 91	-	Input	Supply voltage from the carrier board.
VCCO_64	-	7, 9	Input	High performance I/O bank voltage.
VCCO_65	-	5	Input	High performance I/O bank voltage.
VCCO_66	9, 11	-	Input	High performance I/O bank voltage.

Table 1315: TE0820-02 power rails.

Bank Voltages

Bank	Name on Schematic	Voltage	Range
64 HP	VCCO_64	User	HP: 1.0V to 1.8V
65 HP	VCCO_65	User	HP: 1.0V to 1.8V
66 HP	VCCO_66	User	HP: 1.0V to 1.8V
500 PSMIO	VCCO_PSIO0_500	1.8V	-
501 PSMIO	VCCO_PSIO1_501	3.3V	-
502 PSMIO	VCCO_PSIO2_502	1.8V	-
503 PSCONFIG	VCCO_PSIO3_503	1.8V	-
504 PSDDR	VCCO_PSDDR_504	1.2V	-

Table 1416: TE0820-02 I/O bank voltages.

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Module Variant	MPSoC	RAM	SPI Flash	Temperature Range
TE0820-02-02CG-1E	XCZU2CG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-03CG-1E	XCZU3CG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-02EG-1E	XCZU2EG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-03EG-1E	XCZU3EG-1SFVC784E	1 GByte DDR4	64 MByte	Extended

Table 1517: TE0820-02 variants.

HTML
<!-- currently not in production, but for later usage: TE0820-02-04CG-1E XCZU4CG-1SFVC784E 1 GByte DDR4 64 MByte Extended TE0820-02-04EV-1E XCZU4EV-1SFVC784E 1 GByte DDR4 64 MByte Extended -->

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Parameter	Min	Max	Units	Notes
VIN supply voltage	-0.3	7.0	V	See EN6347QI and TPS82085SIL datasheets.
3.3VIN supply voltage	-0.1	3.75	V	See LCMXO2-256HC and TPS27082L datasheet.
PS I/O supply voltage, VCCO_PSIO	-0.5	3.630	V	Xilinx document DS925
PS I/O input voltage	-0.5	VCCO_PSIO + 0.55	V	Xilinx document DS925
HP I/O bank supply voltage, VCCO	-0.5	2.0	V	Xilinx document DS925
HP I/O bank input voltage	-0.55	VCCO + 0.55	V	Xilinx document DS925
Voltage on module JTAG pins	-0.4	VCCO_0 + 0.55	V	VCCO_0 is 1.8V or 3.3V nominal. Xilinx document DS925
Storage temperature	-40	+85	°C	See eMMC datasheet.

Table 1618: Module absolute maximum ratings.

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Parameter	Min	Max	Units	Notes
VIN supply voltage	2.5	6.6	V	See TPS82085S datasheet
3.3VIN supply voltage	2.375	3.6	V	See LCMXO2-256HC datasheet
PS I/O supply voltage, VCCO_PSIO	1.710	3.465	V	Xilinx document DS925
PS I/O input voltage	–0.20	VCCO_PSIO + 0.20	V	Xilinx document DS925
HP I/O banks supply voltage, VCCO	1.14	3.465	V	Xilinx document DS925
HP I/O banks input voltage	-0.20	VCCO + 0.20	V	Xilinx document DS925
Voltage on module JTAG pins	3.135	3.465	V	For a module variant with 3.3V CONFIG bank option

Table 1719: Recommended operating conditions.

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Date	Revision	Notes	PCN Link	Documentation Link
2017-08-17	02	--		TE0820-02
2016-12-23	01	Prototype only		TE0820-01

Table 1820: Hardware revision history table.

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

v.38

Jan Kumann

MGT lanes section added.

2017-08-24

v.36

John John Hartfiel

Correction in the "Key Features" section.

2017-08-21

v.34

John John Hartfiel

"Initial delivery state" section updated.

2017-08-21

v.33

Jan Kumann

HW revision 02 block diagram added.
Power distribution and power-on sequence diagram added.
System Controller CPLD and DDR4 SDRAM sections added.
TRM update to the template revision 1.6
Weight section removed.
Few minor corrections.

2017-08-18

v.7

John Hartfiel

Style changes
Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
Correction of MIO SD Pin-out, System Controller chapter
Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version.

All

Jan Kumann, John Hartfiel

Table 1921: Document change history.

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Trenz Electronic Documentation

Versions Compared

Old Version 37

New Version 38

Key

MGT Lanes

JTAG Interface

Bank Voltages