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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankTypeSignal NameB2B PinFPGA Pin
0505GTR
  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27
  • PS_MGTRRXP0_505, F27
  • PS_MGTRRXN0_505, F28
  • PS_MGTRTXP0_505, E25
  • PS_MGTRTXN0_505, E26
1505GTR
  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21
  • PS_MGTRRXP1_505, D27
  • PS_MGTRRXN1_505, D28
  • PS_MGTRTXP1_505, D23
  • PS_MGTRTXN1_505, D24
2505GTR
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • PS_MGTRRXP0_505, B27
  • PS_MGTRRXN0_505, B28
  • PS_MGTRTXP0_505, C25
  • PS_MGTRTXN0_505, C26
3505GTR
  • B505_RX3_P
  • B505_RX3_N
  • B505_TX3_P
  • B505_TX3_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • PS_MGTRRXP1_505, A25
  • PS_MGTRRXN1_505, A26
  • PS_MGTRTXP1_505, B23
  • PS_MGTRTXN1_505, B24

Table 4: MGT lanes.

 

Below are listed MGT banks reference clock sources.

Clock signalBankSourceFPGA PinNotes
B505_CLK0_P505B2B, JM3-31PS_MGTREFCLK0P_505, F23Supplied by the carrier board.
B505_CLK0_N505B2B, JM3-33PS_MGTREFCLK0N_505, F24Supplied by the carrier board.
B505_CLK1_P505U10, CLK2APS_MGTREFCLK1P_505, E21On-board Si5338A.
B505_CLK1_N505U10, CLK2BPS_MGTREFCLK1N_505, E22On-board Si5338A.
B505_CLK2_P505N/APS_MGTREFCLK2P_505, C21Not connected.
B505_CLK2_N505N/APS_MGTREFCLK2N_505, C22Not connected.
B505_CLK3_P505U10, CLK1APS_MGTREFCLK3P_505, A21On-board Si5338A.
B505_CLK3_N505U10, CLK1BPS_MGTREFCLK3N_505, A22On-board Si5338A.

Table 5: MGT reference clock sources.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

v.3839Jan KumannMGT lanes section added.

2017-08-24

v.36

John Hartfiel

Correction in the  "Key Features" section.

2017-08-21v.34John Hartfiel"Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.

 

2017-08-18

v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version.

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