Page History
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- Xilinx Virtex-7 FPGA module XC7VX330T-2FFG1157C (commercial temperature range)
- PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
- FMC High Pin Count (HPC) connector
- 8 FPGA MGT lanes available on PCIe interface
- DDR3 SO-DIMM SDRAM socket
- 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect, bus width x4)
- External clock input via SMA coaxial connector
- 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
- FPGA configuration through:
- JTAG connector
- SPI Flash memory
- Programmable quad PLL clock generator
- TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner
- On-board high-efficiency DC-DC converters
- Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
- System management and power sequencing
- AES bit-stream encryption
- eFUSE bit-stream encryption
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| FPGA Bank | I/O signals | LVDS pairs | MGT lanes | Bank's reference clock (LVDS pair) |
|---|---|---|---|---|
| 116 | 10 | 5 | 2 | 1 clock-signal from clock synthesizer U9 to bank's pins T6/T5 |
| 117 | 20 | 10 | 4 | 2 clock-signals from clock FMC connector GBTCLK0_M2C and GBTCLK1_M2C (pins J2-D4/J2-D5 and J2-B20/J2-B21) to bank's pins M6/M5 and P6/P5 |
| 118 | 20 | 10 | 4 | 1 reference clock from clock synthesizer U9 to bank's pins F6/F5 1 reference clock from programmable quad PLL clock generator U13 to bank's pins H6/H5 |
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| FPGA bank | I/O signal count | LVDS pairs | MGT lanes | Bank's reference clock (LVDS pair) |
|---|---|---|---|---|
| 114 | 16 | 8 | 4 | - |
| 115 | 18 | 9 | 4 | 1 reference clock from programmable quad PLL clock generator 1 reference clock from PCIe interface J1 to bank's pins AD6/AD5 |
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| CPLD functionality | Interface | Designated CPLD pins | Connected to | Notes |
|---|---|---|---|---|
| I2C interface between on-board peripherals and FPGA | I2C | FPGA_IIC_SDA, pin 24 FPGA_IIC_SCL, pin 25 FPGA_IIC_OE, pin 19 | FPGA bank 16, pin V29 FPGA bank 16, pin W29 FPGA bank 16, pin W26 | VCCIO: 1V8, all with pull-up to 1V8. Following devices and connectors are linked to the FPGA_IIC I2C interface:
Note: FPGA_IIC_OE must kept high for I2C operation. For I2C slave device addresses refer to the component datasheets. |
User I/Os External LVDS pairs | 10 I/Os 5 x differential signaling pairs | EX0_P ... EX4_P EX0_N ... EX4_N | IDC header J7 | Can also be used for single-ended signaling. |
User I/Os Internal LVDS pairs | 13 I/Os 6 x differential signaling pairs | FEX0_P ... FEX5_P FEX0_N ... FEX5_N FEX_DIR (single-ended I/O) | FPGA bank 18 | VCCIO: 1V8 Can also be used for single-ended signaling. FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK). Internal signal assignment: FEX_DIR <= FMC_PRSNT_M2C_L |
| FPGA programming control and state | 2 I/Os | DONE, pin 7 PROGRAM_B, pin 8 | FPGA bank 0, pin V8 FPGA bank 0, pin U8 | VCCIO: 1V8 |
| I2C interface to programmable quad programmable PLL clock generator | I²C | PLL_SCL, pin 14 PLL_SDA, pin 15 | U13, pin 12 U13, pin 19 | VCCIO: 1V8 Only PLL_SDA has 1V8 pull-up. |
| Fan PWM control J4 | 2 I/Os | F1SENSE, pin 99 F1PWM, pin 98 | J4-3 (active low) J4-4 | Internal signal assignment: FEX_5_P <= F1SENSE FEX_5_N => F1PWM |
| Button S2 | 1 I/O | BUTTON, pin 77 | Switch S2 | Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration. |
| LED1 | 1 I/O | LED1, pin 76 | LED D1 (green) | Fast blinking, when FPGA is not programmed. Internal signal assignment: LED1 <= Button S2 or FEX0_P |
PCIe control line RESET_B | 1 I/O | PCIE_RSTB, pin 37 | PCIe connector J1-A11 (33R serial resistor) | Internal signal assignment: FEX_4_N <= PCIE_RSTB |
Control Interface to clock synthesizer U9 (TI LMK04828B) | SPI (3 I/Os), 4 I/Os | CLK_SYNTH_SDIO, pin 75 CLK_SYNTH_SCK, pin 74 CLK_SYNTH_RESET, pin 54 CLK_SYNTH_CS, pin 53 CLK_SYNTH_SYNC, pin 52 LMK_STAT0, pin 62 LMK_STAT1, pin 63 | U9, pin 20 U9, pin 19 U9, pin 5 U9, pin 18 U9, pin 6 U9, pin 31 U9, pin 48 | Pull up to 3V3PCI. Internal signal assignment: LMK_SCK <= FEX_1_P LMK_SDIO <= FEX_1_N LMK_CS <= FEX_3_P LMK_SYNC <= EX_3_N LMK_RESET <= FEX_4_P FEX_2_P => LMK_SDIO (FEX_2_N must be 0) LMK_STAT0 and LMK_STAT1 signals are not used. |
| Control Interface to DC-DC converters U3 and U4 (both LT LTM4676) | I2C (2 I/Os), 2 I/Os | LTM_SCL, pin 67 LTM_SDA, pin 66 LTM1_ALERT, pin 65 LTM2_ALERT, pin 64 | U4, pin E6 and U3, pin E6 U4, pin D6 and U3, pin D6 U4, pin E5 U3, pin E5 | 3V3 pull-ups. LTM I2C interface is also accessible trough header J10. LTM1_Alert and LTM2_ALERT signals are not used. |
| Power-on sequence and monitoring | 6 I/Os | EN_1V8, pin 58 PG_1V8, pin 59 EN_FMC_VADJ, pin 60 PG_FMC_VADJ, pin 61 EN_3V3, pin 51 PG_3V3, pin 57 | U20, pin 27 U20, pin 28 U7, pin 27 U7, pin 28 U15, pin 27 U15, pin 28 | Sequence of the supply voltages depend on the System Controller CPLD firmware. EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up. PG signals will not be evaluated. |
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| Clock Source | Schematic Name | Frequency | Clock destination |
|---|---|---|---|
| SMA coaxial connector, J3 | CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N (GND) | User | Clock synthesizer U9, pins 37/38 |
| RAKON P5146LF oscillator, U11 | - | 10.0 MHz | Clock synthesizer U9, pins 43/44 |
| SiTime SiT8208 oscillator, U14 | CLK_25MHz | 25.0 MHz | Quad PLL Programmable quad clock Generator generator U13, pin 3 |
| FMC connector J2, pins H4/H5 | CLK0_P, CLK0_N | User | FPGA bank 17, pins R28/R29 |
| FMC connector J2, pins G2/G3 | CLK1_P, CLK1_N | User | FPGA bank 17, pins P29/P30 |
| FMC connector J2, pins K4/K5 | CLK2_P, CLK2_N | User | FPGA bank 18, pins G30/G31 |
| FMC connector J2, pins J2/J3 | CLK3_P, CLK3_N | User | FPGA bank 18, pins H29/H30 |
| FMC connector J2, pins D4/D5 | GBTCLK0_M2C_P, GBTCLK0_M2C_N | User | FPGA bank 117, pins M6/M5 |
| FMC connector J2, pins B20/B21 | GBTCLK1_M2C_P, GBTCLK1_M2C_N | User | FPGA bank 117, pins P6/P5 |
| PCIe interface J1, pins A13/A14 | PCIE_CLK_P, PCIE_CLK_N | 100 MHz (PCIe spec.) | FPGA bank 115, pins AD6/AD5 |
Table 12: Clock generator sources overview.
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Programmable
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Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U13) on-board. It's output frequencies can be programmed by using the I2C-bus with address 0x70.
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Table 13: I/O pin description of PLL programmable clock generator Si5338A.
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Logic needs to be generated inside the FPGA module to utilize SPI bus correctly.
| LMK04828B (U9) input | signal schematic name | Note |
|---|---|---|
| Status_LD1, Status_LD2 | LMK_STAT0, LMK_STAT1 | Connected to System Controller CPLD, not implemented in current CPLD firmware |
SPI interface and control lines | see section 'System controller CPLD' | The clock synthesizer can be controlled and programmed by the FPGA module via the SPI interface and control lines, which are by-passed through the System Controller CPLD |
| CLKin0, CLKin0* | CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N | Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF. CLKin0 to connected to GND via serial decoupling capacitor 100nF. |
| CLKin1, CLKin1* | CLK_SYNTH_CLKIN1_P, CLK_SYNTH_CLKIN1_N | Input reference clock signal from programmable quad |
| clock generator Si5338A (U13) via serial decoupling capacitor 100nF. | ||
| OSCin, OSCin* | - | Signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz |
| LMK04828B (U9) output | signal schematic name | Note |
|---|---|---|
| DCLKout0, DCLKout0* | CLK_SYNTH_DCLKOUT0_P, CLK_SYNTH_DCLKOUT0_N | Reference clock signal to FPGA bank 15 pins AD29/AE29 |
| SDCLKout1, SDCLKout1* | CLK_SYNTH_SDCLKOUT1_P, CLK_SYNTH_SDCLKOUT1_N | Reference clock signal to FPGA bank 15 pins AE31/AF31 |
| DCLKout2, DCLKout2* | CLKIN_5338_P, CLKIN_5338_N | Reference clock signal to programmable quad |
clock generator Si5338A (U13) (100 nF decoupling capacitors and 100Ω termination resistor) | ||
| DCLKout4, DCLKout4* | CLK_SYNTH_DCLKOUT4_P, CLK_SYNTH_DCLKOUT4_N | Reference clock signal to FPGA bank 115 MGT, pins T6/T5 |
| SDCLKout7, SDCLKout7* | CLK_SYNTH_SDCLKOUT7_P, CLK_SYNTH_SDCLKOUT7_N | Reference clock signal to FPGA bank 118 MGT, pins F6/F5 |
| OSCout0, OSCout0* | CLK_SYNTH_CLKIN2_P, CLK_SYNTH_CLKIN2_N | Reference clock signal to FPGA bank 18, pins J30/J31 (100 nF decoupling capacitors) |
Table 14: Pin description of clock synthesizer TI LMK04828B.
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Figure 3: FPGA board TEC0330-03 Powerpower-On on sequence diagram.
Bank Voltages
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Overview
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