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Table 9: JTAG Interface on TEC0330 board.

SO-DIMM Socket for DDR3 SDRAM

The TEC0330 board supports additional DDR3 SO-DIMM (204-pin) via 204-pin SO-DIMM socked U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.

The reference clock signal for the DDR3 interface is generated by the quad programmable reference clock U13 and is applied to bank 35.

There is also a I2C interface between the System Controller CPLD and the DDR3 SDRAM memory:

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On-board Peripherals

System Controller CPLD

The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA module and to display its programming state.

CPLD bankCPLD bank's VCCIO
03V3PCI
13V3PCI
23V3PCI
31V8

Table 11: VCCIO voltages of CPLD banks.

Following table describes the interfaces and functionalities of the System Controller CPLD, which are not described elsewhere in this TRM:

CPLD functionalityInterfaceDesignated CPLD pinsConnected to
Notes
I2C interface between on-board peripherals and FPGAI2C

FPGA_IIC_SDA, pin 24

FPGA_IIC_SCL, pin 25

FPGA_IIC_OE, pin 19

FPGA bank 16, pin V29

FPGA bank 16, pin W29

FPGA bank 16, pin W26

VCCIO: 1V8, all with pull-up to 1V8.

Following devices and connectors are linked to the FPGA_IIC I2C interface:

  • DC-DC converter U3 and U4 (LT LTM4676)
  • Programmable quad clock generator U13
  • FMC connector J2
  • PCIe connector J1

Note: FPGA_IIC_OE must kept high for I2C operation.

For I2C slave device

Table 10: I2C-interface between SC CPLD and DDR3 SDRAM memory.

System Controller CPLD

The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA module and to display its programming state.

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Table 11: VCCIO voltages of CPLD banks.

Following table describes the interfaces and functionalities of the System Controller CPLD, which are not described elsewhere in this TRM:

CPLD functionalityInterfaceDesignated CPLD pinsConnected to
Notes
I2C interface between on-board peripherals and FPGAI2C

FPGA_IIC_SDA, pin 24

FPGA_IIC_SCL, pin 25

FPGA_IIC_OE, pin 19

FPGA bank 16, pin V29

FPGA bank 16, pin W29

FPGA bank 16, pin W26

VCCIO: 1V8, all with pull-up to 1V8.

Following devices and connectors are linked to the FPGA_IIC I2C interface:

  • DC-DC converter U3 and U4 (LT LTM4676)
  • Programmable quad clock generator U13
  • FMC connector J2
  • PCIe connector J1

Note: FPGA_IIC_OE must kept high for I2C operation.

For I2C slave device addresses refer to the component datasheets.

User I/Os

External LVDS pairs

10 I/Os

5 x differential signaling pairs

EX0_P ... EX4_P

EX0_N ... EX4_N

IDC header J7

Can also be used for single-ended signaling.

User I/Os

Internal LVDS pairs

13 I/Os

6 x differential signaling pairs

FEX0_P ... FEX5_P

FEX0_N ... FEX5_N

FEX_DIR (single-ended I/O)

FPGA bank 18

VCCIO: 1V8

Can also be used for single-ended signaling.

FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK).

Internal signal assignment:

FEX_DIR <= FMC_PRSNT_M2C_L

FPGA programming control and state2 I/Os

DONE, pin 7

PROGRAM_B, pin 8

FPGA bank 0, pin V8

FPGA bank 0, pin U8

VCCIO: 1V8
I2C interface to programmable quad clock generatorI²C

PLL_SCL, pin 14

PLL_SDA, pin 15

U13, pin 12

U13, pin 19

VCCIO: 1V8

Only PLL_SDA has 1V8 pull-up.

Fan PWM control J42 I/Os

F1SENSE, pin 99

F1PWM, pin 98

J4-3 (active low)

J4-4

Internal signal assignment:

FEX_5_P <= F1SENSE

FEX_5_N => F1PWM

Button S21 I/OBUTTON, pin 77Switch S2Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration.
LED11 I/OLED1, pin 76LED D1 (green)

Fast blinking, when FPGA is not programmed.

Internal signal assignment:

LED1 <= Button S2 or FEX0_P

PCIe control line RESET_B

1 I/OPCIE_RSTB, pin 37PCIe connector J1-A11 (33R serial resistor)

Internal signal assignment:

FEX_4_N <= PCIE_RSTB

Control Interface to clock synthesizer U9 (TI LMK04828B)

SPI (3 I/Os),

4 I/Os

CLK_SYNTH_SDIO, pin 75

CLK_SYNTH_SCK, pin 74

CLK_SYNTH_RESET, pin 54

CLK_SYNTH_CS, pin 53

CLK_SYNTH_SYNC, pin 52

LMK_STAT0, pin 62

LMK_STAT1, pin 63

U9, pin 20

U9, pin 19

U9, pin 5

U9, pin 18

U9, pin 6

U9, pin 31

U9, pin 48

Pull up to 3V3PCI.

Internal signal assignment:

LMK_SCK <= FEX_1_P

LMK_SDIO <= FEX_1_N

LMK_CS <= FEX_3_P

LMK_SYNC <= EX_3_N

LMK_RESET <= FEX_4_P

FEX_2_P => LMK_SDIO (FEX_2_N must be 0)

LMK_STAT0 and LMK_STAT1 signals are not used.

Control Interface to DC-DC converters U3 and U4 (both LT LTM4676)

I2C (2 I/Os),

2 I/Os

LTM_SCL, pin 67

LTM_SDA, pin 66

LTM1_ALERT, pin 65

LTM2_ALERT, pin 64

U4, pin E6 and U3, pin E6

U4, pin D6 and U3, pin D6

U4, pin E5

U3, pin E5

3V3 pull-ups.

LTM I2C interface is also accessible trough header J10.

LTM1_Alert and LTM2_ALERT signals are not used.

Power-on sequence and monitoring6 I/Os

EN_1V8, pin 58

PG_1V8, pin 59

EN_FMC_VADJ, pin 60

PG_FMC_VADJ, pin 61

EN_3V3, pin 51

PG_3V3, pin 57

U20, pin 27

U20, pin 28

U7, pin 27

U7, pin 28

U15, pin 27

U15, pin 28

Sequence of the supply voltages depend on the System Controller CPLD firmware.

EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.

PG signals will not be evaluated.

Table 12: Overview of the System Controller CPLD functions.

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functions.

SO-DIMM Socket for DDR3 SDRAM

The TEC0330 board supports additional DDR3 SO-DIMM via 204-pin SO-DIMM socked U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.

The reference clock signal for the DDR3 interface is generated by the quad programmable reference clock U13 and is applied to bank 35.

There is also a I2C interface between the System Controller CPLD and the DDR3 SDRAM memory:

Interface signals schematic nameSystem Controller CPLD pinDDR3 memory interface pin
DDR3_SDABank 2, pin 48Pin 200 (3V3PCI pull-up)
DDR3_SCLBank 2, pin 49Pin 202 (3V3PCI pull-up)

Table 10: I2C-interface between SC CPLD and DDR3 SDRAM memory.

Quad SPI Flash Memory

An 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Clock sources

The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.

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List of on-board and external reference clock signals of the TE0330 board:

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LMK04828B (U9) inputsignal schematic nameNote
Status_LD1, Status_LD2LMK_STAT0, LMK_STAT1Connected to System Controller CPLD, not implemented in current CPLD firmware

SPI interface and control lines

see section 'System controller CPLD'The clock synthesizer can be controlled and programmed by the FPGA module via the SPI interface and control lines, which are by-passed through the System Controller CPLD
CLKin0, CLKin0*

CLK_SYNTH_CLKIN0_P,

CLK_SYNTH_CLKIN0_N

Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF.

CLKin0 to connected to GND via serial decoupling capacitor 100nF. 

CLKin1, CLKin1*

CLK_SYNTH_CLKIN1_P,

CLK_SYNTH_CLKIN1_N

Input reference clock signal from programmable quad clock generator Si5338A (U13) via serial decoupling capacitor 100nF.
OSCin, OSCin*-Signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz
LMK04828B (U9) outputsignal schematic nameNote
DCLKout0, DCLKout0*

CLK_SYNTH_DCLKOUT0_P,

CLK_SYNTH_DCLKOUT0_N

Reference clock signal to FPGA bank 15 pins AD29/AE29
SDCLKout1, SDCLKout1*

CLK_SYNTH_SDCLKOUT1_P,

CLK_SYNTH_SDCLKOUT1_N

Reference clock signal to FPGA bank 15 pins AE31/AF31
DCLKout2, DCLKout2*

CLKIN_5338_P,

CLKIN_5338_N

Reference clock signal to programmable quad clock generator Si5338A (U13)

(100 nF decoupling capacitors and 100Ω termination resistor)

DCLKout4, DCLKout4*

CLK_SYNTH_DCLKOUT4_P,

CLK_SYNTH_DCLKOUT4_N

Reference clock signal to FPGA bank 115 MGT, pins T6/T5
SDCLKout7, SDCLKout7*

CLK_SYNTH_SDCLKOUT7_P,

CLK_SYNTH_SDCLKOUT7_N

Reference clock signal to FPGA bank 118 MGT, pins F6/F5
OSCout0, OSCout0*

CLK_SYNTH_CLKIN2_P,

CLK_SYNTH_CLKIN2_N

Reference clock signal to FPGA bank 18, pins J30/J31

(100 nF decoupling capacitors)

Table 15: Pin description of clock synthesizer TI LMK04828B.

32 MByte Quad SPI Flash Memory

clock signal to FPGA bank 18, pins J30/J31

(100 nF decoupling capacitors)

Table 15: Pin description of clock synthesizer TI LMK04828BAn 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Power and Power-On Sequence

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 Power Input
Typical Current
12V (J5)TBD
3V3PCI (J1)TBD

Table 16: Maximum current of Typical power suppliesconsumption. TBD  - To Be Determined.

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DateRevisionContributorsDescription

 

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

 Jan Kumann
  • MGT Lanes section added
  • Fixed signal names in JTAG section.
  • On-board peripherals section added.
  • Weight section removed.

2017-08-30

v.15

Jan Kumann
  • Block diagram changed.
  • Physical dimensions image changed.
  • New product images.
  • Corrections in content.
  • Template revision added.
2017-03-15
v.3
 Ali Naseri
Initial TRM release.

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