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MGT (Multi Gigabit Transceiver) lane consists of one receive and one transmit (RX/TX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin connection and FPGA pin connection information:.

FPGA to FMC Connector MGT lanes

Lane	FPGA Bank	Type	Signal Name	FMC FPGA PinFPGA	FMC Pin
0	117	GTH	DP0_M2C_P DP0_M2C_N DP0_C2M_P DP0_C2M_N	J2A-C6 J2A-C7 J2A-C2 J2A-C3	MGTHRXP0_117, N4 MGTHRXN0_117, N3 MGTHTXP0_117, M2 MGTHTXN0_117, M1	J2A-C6 J2A-C7 J2A-C2 J2A-C3
1	117	GTH	DP1_M2C_P DP1_M2C_N DP1_C2M_P DP1_C2M_N	J2A-A2 J2A-A3 J2A-A22 J2A-A23	MGTHRXP1_117, L4 MGTHRXN1_117, L3 MGTHTXP1_117, K2 MGTHTXN1_117, K1	J2A-A2 J2A-A3 J2A-A22 J2A-A23
2	117	GTH	DP2_M2C_P DP2_M2C_N DP2_C2M_P DP2_C2M_N	J2A-A6 J2A-A7 J2A-A26 J2A-A27	MGTHRXP2_117, K6 MGTHRXN2_117, MGTHRXP2_117, K6 MGTHRXN2_117, K5 MGTHTXP2_117, H2 MGTHTXN2_117, H1	J2A-A6 J2A-A7 J2A-A26 J2A-A27
3	117	GTH	DP3_M2C_P DP3_M2C_N DP3_C2M_P DP3_C2M_NJ2A-A10 J2A-A11 J2A-A30 J2A-A31	MGTHRXP3_117, J4 MGTHRXN3_117, J3 MGTHTXP3_117, F2 MGTHTXN3_117, F1	J2A-A10 J2A-A11 J2A-A30 J2A-A31
4	118	GTH	DP4_M2C_P DP4_M2C_N DP4_C2M_P DP4_C2M_N J2A-A14 J2A-A15 J2A-A34 J2A-A35	MGTHRXP0_118, G4 MGTHRXN0_118, G3 MGTHTXP0_118, D2 MGTHTXN0_118, D1	J2A-A14 J2A-A15 J2A-A34 J2A-A35

Table 8 Table 8: FPGA to FMC connector MGT lanes overview (continue on next page).

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FPGA to FMC Connector MGT lanes (continued)

Lane	FPGA Bank	Type	Signal Name	FMC FPGA PinFPGA	FMC Pin
5	118	GTH	DP5_M2C_P DP5_M2C_N DP5_C2M_P DP5_C2M_N	J2A-A18 J2A-A19 J2A-A38 J2A-A39	MGTHRXP1_118, E4 MGTHRXN1_118, E3 MGTHTXP1_118, C4 MGTHTXN1_118, C3	J2A-A18 J2A-A19 J2A-A38 J2A-A39
6	118	GTH	DP6_M2C_P DP6_M2C_N DP6_C2M_P DP6_C2M_N J2A-B16 J2A-B17 J2A-B36 J2A-B37	MGTHRXP2_118, D6 MGTHRXN2_118, D5 MGTHTXP2_118, B2 MGTHTXN2_118, B1	J2A-B16 J2A-B17 J2A-B36 J2A-B37
7	118	GTH	DP7_M2C_P DP7_M2C_N DP7_C2M_P DP7_C2M_N	J2A-B12 J2A-B13 J2A-B32 J2A-B33	MGTHRXP3_MGTHRXP3_118, B6 MGTHRXN3_118, B5 MGTHTXP3_118, A4 MGTHTXN3_118, A3	J2A-B12 J2A-B13 J2A-B32 J2A-B33
8	116	GTH	DP8_M2C_P DP8_M2C_N DP8_C2M_P DP8_C2M_N J2A-B8 J2A-B9 J2A-B28 J2A-B29	MGTHRXP2_116, U4 MGTHRXN2_116, U3 MGTHTXP2_116, T2 MGTHTXN2_116, T1	J2A-B8 J2A-B9 J2A-B28 J2A-B29
9	116	GTH	DP9_M2C_P DP9_M2C_N DP9_C2M_P DP9_C2M_N	MGTHRXP3_116, R4 MGTHRXN3_116, R3 MGTHTXP3_116, P2 MGTHTXN3_116, P1	J2A-B4 J2A-B5 J2A-B24 J2A-B25	MGTHRXP3_116, R4 MGTHRXN3_116, R3 MGTHTXP3_116, P2 MGTHTXN3_116, P1

Table 8: FPGA to FMC connector MGT lanes overview.

-B24
J2A-B25

Table 8: FPGA to FMC connector MGT lanes overview.

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FPGA to PCIe Connector MGT lanes

Lane	FPGA Bank	Type	Signal Name	FPGA Pin	PCIe Pin
0	115	GTH	PER0_P PER0_N PET0_P PET0_N	MGTHRXP3_115, AB2 MGTHRXN3_115, AB1 MGTHTXP3_115, AC4 MGTHTXN3_115, AC3	J1-A16 J1-A17 J1-B14 J1-B15
1	115	GTH	PER1_P PER1_N PET1_P PET1_N	MGTHRXP2_115, AD2 MGTHRXN2_115, AD1 MGTHTXP2_115, AE4 MGTHTXN2_115, AE3	J1-A21 J1-A22 J1-B19 J1-B20
2	115	GTH	PER2_P PER2_N PET2_P PET2_N	MGTHRXP1_115, AF2 MGTHRXN1_115, AF1 MGTHTXP1_115, AF6 MGTHTXN1_115, AF5	J1-A25 J1-A26 J1-B23 J1-B24
3	115	GTH	PER3_P PER3_N PET3_P PET3_N	MGTHRXP0_115, AH2 MGTHRXN0_115, AH1 MGTHTXP0_115, AG4 MGTHTXN0_115, AG3	J1-A29 J1-A30 J1-B27 J1-B28
4	114	GTH	PER4_P PER4_N PET4_P PET4_N	MGTHRXP3_114, AK2 MGTHRXN3_114, AK1 MGTHTXP3_114, AJ4 MGTHTXN3_114, AJ3	J1-A35 J1-A36 J1-B33 J1-B34
5	114	GTH	PER5_P PER5_N PET5_P PET5_N	MGTHRXP2_114, AM2 MGTHRXN2_114, AM1 MGTHTXP2_114, AL4 MGTHTXN2_114, AL3	J1-A39 J1-A40 J1-B37 J1-B38
6	114	GTH	PER6_P PER6_N PET6_P PET6_N	MGTHRXP1_114, AN4 MGTHRXN1_114, AN3 MGTHTXP1_114, AM6 MGTHTXN1_114, AM5	J1-A43 J1-A44 J1-B41 J1-B42
7	114	GTH	PER7_P PER7_N PET7_P PET7_N	MGTHRXP0_114, AP2 MGTHRXN0_114, AP1 MGTHTXP0_114, AP6 MGTHTXN0_114, AP5	J1-A47 J1-A48 J1-B45 J1-B46

Table 9: FPGA to PCIe connector MGT lanes overview.

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JTAG Interfaces

TEC0330 board JTAG interfaces accessing the FPGA or the System Controller CPLD:

JTAG interface	JTAG signals schematic name	JTAG connector pins	Connected to
CPLD JTAG VCCIO: 3V3PCI Connector: J8	CPLD_JTAG_TMS	J8-1	SC CPLD, bank 0, pin 90
	CPLD_JTAG_TDI	J8-2	SC CPLD, bank 0, pin 94
	CPLD_JTAG_TDO	J8-3	SC CPLD, bank 0, pin 95
	CPLD_JTAG_TCK	J8-4	SC CPLD, bank 0, pin 91

FPGA JTAG VCCIO: 1V8 Connector: J9	FPGA_JTAG_TMS	J9-4	FPGA, bank 0, pin N9
	FPGA_JTAG_TCK	J9-6	FPGA, bank 0, pin M8
	FPGA_JTAG_TDO	J9-8	FPGA, bank 0, pin N8
	FPGA_JTAG_TDI	J9-10	FPGA, bank 0, pin L8

FMC JTAG VCCIO: 3.3VPCI Connector: J2	FMC_TRST	J2-D34	SC CPLD, bank 2, pin 36
	FMC_TCK	J2-D29	SC CPLD, bank 2, pin 27
	FMC_TMS	J2-D33	SC CPLD, bank 2, pin 28
	FMC_TDI	J2-D30	SC CPLD, bank 2, pin 31
	FMC_TDO	J2-D31	SC CPLD, bank 2, pin 32

Table 910: JTAG Interface on TEC0330 board.

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Interface signals schematic name	System Controller CPLD pin	DDR3 memory interface pin
DDR3_SDA	Bank 2, pin 48	Pin 200 (3V3PCI pull-up)
DDR3_SCL	Bank 2, pin 49	Pin 202 (3V3PCI pull-up)

Table 1013: I²C-interface between SC CPLD and DDR3 SDRAM memory.

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Clock Source	Schematic Name	Frequency	Clock destination
SMA coaxial connector, J3	CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N (GND)	User	Clock synthesizer U9, pins 37/38
RAKON P5146LF oscillator, U11	-	10.0 MHz	Clock synthesizer U9, pins 43/44
SiTime SiT8208 oscillator, U14	CLK_25MHz	25.0 MHz	Programmable quad clock generator U13, pin 3
FMC connector J2, pins H4/H5	CLK0_P, CLK0_N	User	FPGA bank 17, pins R28/R29
FMC connector J2, pins G2/G3	CLK1_P, CLK1_N	User	FPGA bank 17, pins P29/P30
FMC connector J2, pins K4/K5	CLK2_P, CLK2_N	User	FPGA bank 18, pins G30/G31
FMC connector J2, pins J2/J3	CLK3_P, CLK3_N	User	FPGA bank 18, pins H29/H30
FMC connector J2, pins D4/D5	GBTCLK0_M2C_P, GBTCLK0_M2C_N	User	FPGA bank 117, pins M6/M5
FMC connector J2, pins B20/B21	GBTCLK1_M2C_P, GBTCLK1_M2C_N	User	FPGA bank 117, pins P6/P5
PCIe interface J1, pins A13/A14	PCIE_CLK_P, PCIE_CLK_N	100 MHz (PCIe spec.)	FPGA bank 115, pins AD6/AD5

Table 1314: Clock generator sources overview.

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Si5338A (U13) input	Signal schematic name	Notes
IN1/IN2	CLKIN_5338_C_P, CLKIN_5338_C_N	Reference clock signal from clock synthesizer U9 (100 nF decoupling capacitors and 100Ω termination resistor)
IN3	Reference clock oscillator input, SiTime SiT8208AI (U14).	25.0 MHz fixed frequency
IN4/IN6	Connected to the GND.	LSB (pin 'IN4') of the default I²C-adress 0x70 is zero
IN5	Not connected	-
Si5338A (U13) output	Signal schematic name	Notes
CLK0 A/B	DDR3_CLK_P, DDR3_CLK_N	DDR3-RAM reference clock signal to FPGA bank 35
CLK1 A/B	MGTCLK_5338_C_P, MGTCLK_5338_C_N	Reference clock signal to FPGA bank 115 MGT (100 nF decoupling capacitors and 100Ω termination resistor)
CLK2 A/B	LMK_CLK_P, LMK_CLK_N	Input clock signal to clock synthesizer U9 (100 nF decoupling capacitors)
CLK3 A/B	MGTCLK2_5338_C_P, MGTCLK2_5338_C_N	Reference clock signal to FPGA bank 118 MGT (100 nF decoupling capacitors and 100Ω termination resistor)

Table 1415: I/O pin description of programmable clock generator Si5338A.

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LMK04828B (U9) input	signal schematic name	Note
Status_LD1, Status_LD2	LMK_STAT0, LMK_STAT1	Connected to System Controller CPLD, not implemented in current CPLD firmware
SPI interface and control lines	see section 'System controller CPLD'	The clock synthesizer can be controlled and programmed by the FPGA module via the SPI interface and control lines, which are by-passed through the System Controller CPLD
CLKin0, CLKin0*	CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N	Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF. CLKin0 to connected to GND via serial decoupling capacitor 100nF.
CLKin1, CLKin1*	CLK_SYNTH_CLKIN1_P, CLK_SYNTH_CLKIN1_N	Input reference clock signal from programmable quad clock generator Si5338A (U13) via serial decoupling capacitor 100nF.
OSCin, OSCin*	-	Signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz
LMK04828B (U9) output	signal schematic name	Note
DCLKout0, DCLKout0*	CLK_SYNTH_DCLKOUT0_P, CLK_SYNTH_DCLKOUT0_N	Reference clock signal to FPGA bank 15 pins AD29/AE29
SDCLKout1, SDCLKout1*	CLK_SYNTH_SDCLKOUT1_P, CLK_SYNTH_SDCLKOUT1_N	Reference clock signal to FPGA bank 15 pins AE31/AF31
DCLKout2, DCLKout2*	CLKIN_5338_P, CLKIN_5338_N	Reference clock signal to programmable quad clock generator Si5338A (U13) (100 nF decoupling capacitors and 100Ω termination resistor)
DCLKout4, DCLKout4*	CLK_SYNTH_DCLKOUT4_P, CLK_SYNTH_DCLKOUT4_N	Reference clock signal to FPGA bank 115 MGT, pins T6/T5
SDCLKout7, SDCLKout7*	CLK_SYNTH_SDCLKOUT7_P, CLK_SYNTH_SDCLKOUT7_N	Reference clock signal to FPGA bank 118 MGT, pins F6/F5
OSCout0, OSCout0*	CLK_SYNTH_CLKIN2_P, CLK_SYNTH_CLKIN2_N	Reference clock signal to FPGA bank 18, pins J30/J31 (100 nF decoupling capacitors)

Table 1516: Pin description of clock synthesizer TI LMK04828B.

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Power Input	Typical Current
12V (J5)	TBD
3V3PCI (J1)	TBD

Table 1617: Typical power consumption. TBD - To Be Determined.

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Bank	Schematic Name	Voltage	Range	Note
0	1V8	1.8V	HP: 1.2V to 1.8V	Config bank (fixed to 1.8V) / JTAG interface
14	1V8	1.8V	HP: 1.2V to 1.8V	QSPI flash memory interface
15	1V8	1.8V	HP: 1.2V to 1.8V	Reference clock input
16	1V8	1.8V	HP: 1.2V to 1.8V	I²C interface of FPGA
17	1V8	1.8V	HP: 1.2V to 1.8V	Reference clock input
18	1V8	1.8V	HP: 1.2V to 1.8V	Reference clock input / I/O's to CPLD
34	VCC1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
35	VCC1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
36	VCC1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
114 115 116 117 118	MGTAVCC_FPGA MGTVCCAUX_FPGA MGTAVTT_FPGA	1.0V 1.8V 1.2V	MGT bank supply voltage MGT bank auxiliary supply voltage MGT bank termination circuits voltage	MGT banks with Xilinx GTH transceiver units
19	1V8	1.8V	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs
37	1V8	1.8V	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs
38	1V8	1.8V	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs
39	VIO_B_FMC	user	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs

Table 1718: Range of FPGAs bank voltages.

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Connector / Pin	Voltage	Direction	Notes
J4, pin 2	12V (filtered)	Output	4-wire PWM fan connector supply voltage
J6, pin 2	5V (filtered)	Output	Cooling fan M1 supply voltage
J8, pin 6	3V3PCI	Output	VCCIO CPLD JTAG
J9, pin 2	1V8	Output	VCCIO FPGA JTAG
J2, pin C35 / C37	12V	Output	VCCIO FMC
J2, pin D32	3V3PCI	Output	VCCIO FMC
J2, pin D36 / D38 / D39 / D40	3V3FMC	Output	VCCIO FMC
J2, pin H1	VREF_A_M2C	Input	VREF voltage for bank 37 / 38
J2, pin K1	VREF_B_M2C	Input	VREF voltage for bank 39
J2, pin J39 / J40	VIO_B_FMC	Input	PL I/O voltage bank 39 (VCCO)
J2, pin H40 / G39 / F40 / E39	FMC_VADJ	Output	VCCIO FMC (fixed to 1.8V)
J1, pin A10 / A11 / B8	3V3PCI	Input	PCIe interface supply voltage
J5, pin 1 / 2 / 3	12V	Input	Main power supply connector

Table 1819: Power rails and corresponding connectors of the FPGA board.

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Parameter	Min	Max	Units	Notes	Notes
12V power supply voltage	11.4	12.6	V	12V ± 5 %	ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
PL I/O voltage for HP banks	-0.55	VCCO_X + 0.55	V	-	Xilinx datasheet DS183
GTH transceivers	-0.5	1.26	V	-	Xilinx datasheet DS183
Voltage on System Controller CPLD pins	-0.3	3.6	V	-	MachXO2 family datasheet
Storage temperature	-55	+125	°C	-	MachXO2 family datasheet

Table 1920: Absolute maximum ratings.

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Parameter	Min	Max	Units	Notes	Reference Document
12V power supply voltage	11.4	12.6	V	12V ± 5 %	ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
PL I/O voltage for HP banks	-0.2	VCCO_X + 0.2	V	-	Xilinx datasheet DS183
GTH transceivers	(*)	(*)	-	-	Xilinx datasheet DS183
Voltage on System Controller CPLD pins	3.135	3.6	V	-	MachXO2 family datasheet

Table 2021: Recommended operation conditions.

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Date	Revision	Notes	PCN	Documentation
-	03	First production release	-	-
2015-11-05	02	Prototype	-	-
-	01	Prototype	-	-

Table 2122: Hardware revision history.

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Jan Kumann

MGT Lanes section added
Fixed signal names in JTAG section.
On-board peripherals section added.
Weight section removed.

2017-08-30

v.15

Jan Kumann

Block diagram changed.
Physical dimensions image changed.
New product images.
Corrections in content.
Template revision added.

2017-03-15

v.3

Ali Naseri

Initial TRM release.

Table 2223: Document change history.

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