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FPGA to PCIe Connector MGT lanes
| Lane | FPGA Bank | Type | Signal Name | FPGA Pin | PCIe Pin |
|---|
| 0 | 115 | GTH | | - MGTHRXP3_115, AB2
- MGTHRXN3_115, AB1
- MGTHTXP3_115, AC4
- MGTHTXN3_115, AC3
| |
| 1 | 115 | GTH | | - MGTHRXP2_115, AD2
- MGTHRXN2_115, AD1
- MGTHTXP2_115, AE4
- MGTHTXN2_115, AE3
| |
| 2 | 115 | GTH | | - MGTHRXP1_115, AF2
- MGTHRXN1_115, AF1
- MGTHTXP1_115, AF6
- MGTHTXN1_115, AF5
| |
| 3 | 115 | GTH | | - MGTHRXP0_115, AH2
- MGTHRXN0_115, AH1
- MGTHTXP0_115, AG4
- MGTHTXN0_115, AG3
| |
| 4 | 114 | GTH | | - MGTHRXP3_114, AK2
- MGTHRXN3_114, AK1
- MGTHTXP3_114, AJ4
- MGTHTXN3_114, AJ3
| |
| 5 | 114 | GTH | | - MGTHRXP2_114, AM2
- MGTHRXN2_114, AM1
- MGTHTXP2_114, AL4
- MGTHTXN2_114, AL3
| |
| 6 | 114 | GTH | | - MGTHRXP1_114, AN4
- MGTHRXN1_114, AN3
- MGTHTXP1_114, AM6
- MGTHTXN1_114, AM5
| |
| 7 | 114 | GTH | | - MGTHRXP0_114, AP2
- MGTHRXN0_114, AP1
- MGTHTXP0_114, AP6
- MGTHTXN0_114, AP5
| |
Table 9: FPGA to PCIe connector MGT lanes overview.
JTAG Interfaces
TEC0330 board JTAG interfaces accessing the FPGA or the System Controller CPLD:
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