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The TEC0330 FPGA board is also a PCI Express card designed to fit in computing into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. 8 See next section for FPGA MGT lanes are routed to the PCIe interface composed of RX/TX LVDS pairs for each lane:

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MGT lanes

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1 reference clock from  programmable quad clock generator
U13 to bank's pins AB6/AB5

1 reference clock from PCIe interface J1 to bank's pins AD6/AD5

Table 7: MGT lanes available on PCIe interface.

MGT Lanes

 MGT (Multi Gigabit Transceiver) lane consists of one receive and one transmit (RX/TX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin connection and FPGA pin connection information.

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 Table 8: FPGA to FMC connector MGT lanes overview.

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FPGA to PCIe Connector MGT lanes 

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