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| Info |
|---|
2 Firmware variants with swapped external reset input and output direction are available. See Watchdog section of this document. |
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| Modus | Condition |
|---|---|
| Slow Blink | If PS_POR_B is low and appr. 16s after PS_POR_B goes up |
| FPGA_IO | User defined, appr. 30s long 16s after PS_POR_B goes up and as long as PS_POR_B is high |
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