Page History
...
The I/O signals are routed from the FPGA I/O banks to the FMC connector as LVDS pairs:
| FPGA Bank | I/O Signals | LVDS pairs |
|---|
| Bank Voltage (VCCO) | Notes | |||
|---|---|---|---|---|
| Bank 19 | 92 | 46 | 1.8V | - |
| Bank 39 | 42 | 21 | VIO_B_FMC | Bank voltage VIO_B_FMC must be supplied by FMC connector pins J2-J39, J2-K40. Bank's VREF_B_M2C signal is routed to the FMC connector pin J2-K1 (external reference voltage). |
| Bank 37 | 34 | 17 | 1.8V | Bank's VREF_A_M2C signal is routed to the FMC connector pin J2-H1 (external reference voltage). |
| Bank 38 | 34 | 17 | 1.8V | Bank's VREF_A_M2C signal is routed to the FMC connector pin J2-H1 (external reference voltage). |
Table 2: Overview of the FPGA I/O bank signals routed to the FMC.
...
Overview
Content Tools