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The module has following reference clock signals provided by on-board oscillators:
| Source | Signal | Frequency | Destination | Pin Name | Notes |
|---|---|---|---|---|---|
| U14 | PS_CLK | 52.000000 MHz | U1 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U14 | OTG-RCLK | 52.000000 MHz | U18 | REFCLK | USB3320C PHY reference clock. |
| U7 | OSCI | 12.000000 MHz | U3 | OSCI | FT2232H oscillator input. |
Table x: Reference clock signals.
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Power-On Sequence
There is no sequence...
Variants Currently in Production
| Module Variant | Xilinx Zynq SoC | DDR3L SDRAM | ARM Cores | PL Cells | LUTs | Flip-Flops | Block RAM | DSP Slices |
|---|---|---|---|---|---|---|---|---|
| TE0723-02 | XC7Z010-1CLG225C | 128 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03M | XC7Z010-1CLG225C | 512 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03-07S-1C | XC7Z007S-1CLG225C | 512 MBytes | Single-core | 23K | 14,4K | 28,8K | 1.8 MBytes | 66 |
Table 8: Module variants.
Technical Specifications
Absolute Maximum Ratings
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Overview
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