Page History
...
Scroll Only (inline) |
---|
Refer to https://wiki.trenz-electronic.de/display/DRAFT/TE0723+TRM for downloadable version of this manual and additional technical documentation of the product.
|
The Trenz Electronic TE0723 is a Arduino compatible FPGA module based on the Xilinx Zynq XC7Z010 SoC.
...
- Xilinx Zynq XC7Z010 SoC, U1
- 4 Gbit DDR3L 256M x 16 SDRAM, U2
- 16 MByte QSPI quad SPI Flash memory, U5
High-speed CMOS logic analog multiplexer/demultiplexer, U10
- 1 MHz low-power operational amplifier, U11
- Dual high-speed USB to multipurpose UART/FIFO, U3
- 0.5A dual-channel current-limited power switch, U21
- Low-power programmable oscillator @ 12.000000 MHz, U7
- 2-Kbit Microwire compatible serial EEPROM, U6
- 10-pin header, J1
- 8-pin header, J2
- 10-pin header, J3
- Analog input header, J4
- 2 x 4-pin header, J5
- PMod 2x6 interface header, J6
- USB host mode jumper, J7
- Micro USB 2.0 Type-B receptacle, J8
- Micro USB 2.0 Type-B receptacle, J9
- Micro SD card connector with detect signal, J10
- Analog input select jumper, J11
- 5V supply power input, J12
- Reset switch, S1
- Red LED, D2
- Green LED, D6
- Green LED, D7
- Ultra-low supply-current voltage monitor, U23
1A PowerSoC DC-DC converter (3.3 V), U20
- 1A PowerSoC DC-DC converter (1.8 V, U19
- 1A PowerSoC DC-DC converter (1.35 V), U16
- Hi-speed USB 2.0 ULPI transceiver, U18
- Low-power programmable oscillator @ 52.000000 MHz, U14
- 1A PowerSoC DC-DC converter (1.0 V), U17
- JTAG interface testpoints, TP1-TP4
Initial Delivery State
Storage device name | IC | Content | Notes |
---|---|---|---|
Quad SPI Flash | U5 | Empty | |
Microwire serial EEPROM | U6 | Empty |
Table 1: Initial delivery state of programmable devices on the module.
...
JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.
Quad SPI Interface
Following line is just an example, change it to your needs.
Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
Note that table column says "Signal Name", it should match the name used on the schematic.
MIO | Signal Name | U14 Pin |
---|---|---|
1 | SPI-CS | C2 |
2 | SPI-DQ0/M0 | D3 |
3 | SPI-DQ1/M1 | D2 |
4 | SPI-DQ2/M2 | C4 |
5 | SPI-DQ3/M3 | D4 |
6 | SPI-SCK/M4 | B2 |
Table x: Quad SPI interface signals and connections.
SD Card Interface
Describe SD Card interface shortly here if the module has one...
FPGA / SoC Pin | Connected To | Signal Name | Notes |
---|---|---|---|
MIO0 | J10-9 | Card detect switch | |
MIO10 | J10-7 | DAT0 | |
MIO11 | J10-3 | CMD | |
MIO12 | J10-5 | CLK | |
MIO13 | J10-8 | DAT1 | |
MIO14 | J10-1 | DAT3 | |
MIO15 | J10-2 | CD/DAT3 |
Default PS MIO Mapping
MIO | Function | Connected To | Notes | MIO | Function | Connected To | Notes |
---|---|---|---|---|---|---|---|
0 | SDCARD | J10-9 | Card detect switch. | 28 | USB-OTG | U18-7 | OTG-DATA4 |
1 | QSPI | U5-1 | SP0-CS | 29 | USB-OTG | U18-31 | OTG-DIR |
2 | QSPI | U5-5 | SPI0-DQ0 | 30 | USB-OTG | U18-29 | OTG-STP |
3 | QSPI | U5-2 | SPI0-DQ1 | 31 | USB-OTG | U18-2 | OTG-NXT |
4 | QSPI | U5-3 | SPI0-DQ2 | 32 | USB-OTG | U18-3 | OTG-DATA0 |
5 | QSPI | U5-7 | SPI0-DQ3 | 33 | USB-OTG | U18-4 | OTG-DATA1 |
6 | QSPI | U5-6 | SPI0-SCK | 34 | USB-OTG | U18-5 | OTG-DATA2 |
7 | GPIO | U18-27 | USB PHY reset | 35 | USB-OTG | U18-6 | OTG-DATA3 |
9 | LED | D2 | Red LED | 36 | USB-OTG | U18-1 | OTG-CLK |
10 | SDCARD | J10-7 | DAT0 | 37 | USB-OTG | U18-9 | OTG-DATA5 |
11 | SDCARD | J10-3 | CMD | 38 | USB-OTG | U18-10 | OTG-DATA6 |
12 | SDCARD | J10-5 | CLK | 39 | USB-OTG | U18-13 | OTG-DATA7 |
13 | SDCARD | J10-8 | DAT1 | 48 | ESP | J5-2 | ESP_TXD |
14 | SDCARD | J10-1 | DAT2 | 49 | ESP | J5-7 | ESP_RXD |
15 | SDCARD | J10-2 | CD/DAT3 | 52 | ESP | J5-6 | MOD_RST |
53 | ESP | J5-3 | ESP_GPIO0 |
USB Interface
ESP Interface
I2C Interface
I2C interface pins from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.
...
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
Microwire Serial EEPROM
U36AA56BT-I/OT...
High-Speed Analog Multiplexer
...