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Date

Revision

Contributors

Description

2017-06-07
Jan KumannMinor formatting
2017-03-02

V.59

Thorsten TrenzCorrected boot mode table
2017-02-10

V58V.58

Thorsten TrenzCorrected PLL initial delivery state
2017-01-25
V.55V55

 

Jan KumannNew block diagram.
2017-01-14

V50V.50

Jan Kumann

Product revision 04 images added.

Formatting changes and small corrections.

2016-11-15

V45V.45

Thorsten Trenz
Added B2B Connector section.
2016-10-18
V40V.40

Ali Naseri

Added table "power rails".
2016-06-28
V.38V38

 

Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann

New overall document layout with shorter table of contents.

Revision 01 PCB pictures replaced with the revision 03 ones.

Fixed link to Master Pin-out Table.

New default MIO mapping table design.

Revised Power-on section.

Added links to related Xilinx online documents.

Physical dimensions pictures revised.

Revision number picture with explanation added.

2016-04-27V33V.33

Thorsten Trenz, Emmanuel Vassilakis

Added table "Recommended Operating Conditions".

Storage Temperature edited.

2016-03-31V10V.10

Philipp Bernhardt, Antti Lukats

Initial version.

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