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By default the TE-0715 supports quad SPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.
MODE Signal State | Boot Mode |
|---|---|
High or open | QSPI |
Low or ground | SD Card |
Table 2: Boot MODE signal description.
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For detailed information about the pin-out, please refer to the Pin-out Table.
MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
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| Clock signal | Bank | Source | FPGA Pin | Notes |
|---|---|---|---|---|
| MGT_CLK0_P | 112 | B2B, JM3-33 | MGTREFCLK0P_112, U9 | Supplied by the carrier board. |
| MGT_CLK0_N | 112 | B2B, JM3-31 | MGTREFCLK0N_112, V9 | Supplied by the carrier board. |
| MGT_CLK1_P | 112 | U10, CLK2A | MGTREFCLK1P_112, U5 | On-board Si5338A. |
| MGT_CLK1_N | 112 | U10, CLK2B | MGTREFCLK1N_112, V5 | On-board Si5338A. |
Table x5: MGT reference clock sources.
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JTAG Signal | B2B Connector Pin |
|---|---|
| TMS | JM2-93 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TCK | JM2-99 |
Table 56: MGT lanes.
| Note |
|---|
| JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
| Page break |
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System Controller CPLD I/O Pins
Special purpose pins are connected to System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| EN1 | Input | Power Enable | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset. |
| PGOOD | Output | Power Good | Active high when all on-module power supplies are working properly. |
| NOSEQ | - | - | No function. |
| RESIN | Input | Reset | Active low reset, gated to POR_B. |
| JTAGEN | Input | JTAG Select | Low for normal operation. |
Table 67: System Controller CPLD I/O pins.
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| Zynq SoC's MIO | Signal Name | U5 Pin |
|---|---|---|
| 1 | SPI0_CS | 1 |
| 2 | SPI0_DQ0/MIO2 | 5 |
| 3 | SPI0_DQ1/MIO3 | 2 |
| 4 | SPI0_DQ2/MIO4 | 3 |
| 5 | SPI0_DQ3/MIO5 | 7 |
| 6 | SPI0_SCK | 6 |
Table 38: Quad SPI interface signals and connections.
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| I2C Device | I2C Address | Notes |
|---|---|---|
| EEPROM | 0x50 | |
| RTC | 0x6F | |
| Battery backed RAM | 0x57 | Integrated into RTC. |
PLL | 0x70 |
On-board Peripherals
System Controller CPLD
The System Controller CPLD (U26) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
DDR Memory
TE0715 module has up to 512-MBytes 1 GBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board QSPI flash quad SPI Flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
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Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using via the I2C bus, slave device address is 0x70.
PLL connection
| I/OU10 Signal | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base carrier board. |
IN3 | 25.000000 MHz | Fixed Reference input clock. |
IN4 | -- | Wired to the GND. |
IN5/IN6 | 125MHz125 MHz | Ethernet PHY output clock. |
CLK0 A/B | - | Not used, disabled. |
CLK1 A/B | - | Not used, disabled. |
CLK2 A/B | 125MHz125 MHz | MGT reference clock 1. |
CLK3A | - | Bank 34 clock input, default disabled, User user clock. |
CLK3B | - | Not used, disabled. |
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