Page History
...
Quad SPI Interface
Quad SPI Flash (U5U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
| Zynq SoC's MIO | Signal Name | U5 Pin |
|---|---|---|
| 1 | SPI0_SPI-CS | 1C2 |
| 2 | SPI0_SPI-DQ0/MIO2M3 | 5D3 |
| 3 | SPI0_SPI-DQ1/MIO3M1 | 2D2 |
| 4 | SPI0_SPI-DQ2/MIO4M2 | 3C4 |
| 5 | SPI0_SPI-DQ3/MIO5M0 | 7D4 |
| 6 | SPI0_SPI-SCK | 6B2 |
Table 8: Quad SPI interface signals and connections.
Clocking
...
PS CLK
...
33.3333 MHz
...
U11
...
PS_CLK
...
PS subsystem main clock.
...
ETH PHY reference
...
25.000000 MHz
...
U9
...
-
...
USB PHY reference
...
52.000000 MHz
...
U15
...
-
...
PLL reference
...
25.000000 MHz
...
U18
...
-
...
GT REFCLK0
...
-
...
B2B
...
U9/V9
...
Externally supplied from baseboard.
...
GT REFCLK1
...
125 MHz
...
U10 Si5338
...
U5/V5
...
Default clock is 125 MHz.
| Page break |
|---|
Default MIO Mapping
...
Ethernet PHY LED2
INTn Signal.
...
| Page break |
|---|
Ethernet Interface
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the IN5 pin of the PLL chip (U10).
Ethernet PHY connection
...
Can be routed via PL to any free PL I/O pin in B2B connector.
This LED is connected to PL via level-shifter implemented in
system controller CPLD.
...
By default the PHY address is strapped to 0x00, alternate
configuration is possible.
...
| Page break |
|---|
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 52.000000 MHz oscillator (U15).
USB PHY connection
...
| Page break |
|---|
SD Card Interface
SD Card interface is connected form the Zynq SoC's PS MIO bank 501 to the B2B connector JM1, signals MIO40 .. MIO45.
Ethernet Interface
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the IN5 pin of the PLL chip (U10).
Ethernet PHY connection
| PHY Pin | Zynq PS | Zynq PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | J3 | Can be routed via PL to any free PL I/O pin in B2B connector. |
| LED1 | - | K8 | Can be routed via PL to any free PL I/O pin in B2B connector. This LED is connected to PL via level-shifter implemented in system controller CPLD. |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY address is strapped to 0x00, alternate configuration is possible. |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | Routed to B2B connector JM3. |
| MDI | - | - | Routed to B2B connector JM1. |
Table 9: Ethernet interface.
| Page break |
|---|
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 52.000000 MHz oscillator (U15).
USB PHY connection
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52.000000 MHz from on board oscillator (U15). |
| REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52.000000 MHz. |
| RESETB | MIO51 | - | Active low reset. |
| CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID | For an A-device connect to the ground, for a B-device leave floating. |
Table 10: USB interface.
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C Address | Notes |
|---|---|---|
| EEPROM | 0x50 | |
| RTC | 0x6F | |
| Battery backed RAM | 0x57 | Integrated into RTC. |
PLL | 0x70 |
Table 11: I2C interface.
On-board Peripherals
System Controller CPLD
The System Controller CPLD (U26) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
DDR Memory
TE0715 module has up to 1 GBytes of DDR3L SDRAM arranged into 32-bit wide memory bus. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board quad SPI Flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
Programmable Clock Generator
There is a Silicon Labs programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed via the I2C bus, slave device address is 0x70.
| U10 Signal | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on carrier board. |
IN3 | 25.000000 MHz | Reference input clock. |
IN4 | - | Wired to the GND. |
IN5/IN6 | 125 MHz | Ethernet PHY output clock. |
CLK0 A/B | - | Not used, disabled. |
CLK1 A/B | - | Not used, disabled. |
CLK2 A/B | 125 MHz | MGT reference clock 1. |
CLK3A | - | Bank 34 clock input, default disabled, user clock. |
CLK3B | - | Not used, disabled. |
Table 12: Programmable clock generator I/Os.
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
Oscillators
The module has following reference clock signals provided by on-board oscillators:
| Source | Signal | Frequency | Destination | Pin Name | Notes |
|---|---|---|---|---|---|
| U18 | CLK | 25.000000 MHz | U10 | IN3 | |
| U9 | CLK | 25.000000 MHz | U7 | XTAL_IN | |
| U11 | PS-CLK | 33.333333 MHz | U5 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U15 | CLK | 52.000000 MHz | U6 | REFCLK | USB3320C PHY reference clock. |
Table 13: Reference clock signals
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
...
PLL
...
On-board Peripherals
System Controller CPLD
The System Controller CPLD (U26) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
DDR Memory
TE0715 module has up to 1 GBytes of DDR3L SDRAM arranged into 32-bit wide memory bus. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board quad SPI Flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
Programmable Clock Generator
There is a Silicon Labs programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed via the I2C bus, slave device address is 0x70.
...
IN1/IN2
...
Externally supplied
...
Needs decoupling on carrier board.
...
IN3
...
25.000000 MHz
...
Reference input clock.
...
IN4
...
-
...
Wired to the GND.
...
IN5/IN6
...
125 MHz
...
Ethernet PHY output clock.
...
CLK0 A/B
...
-
...
Not used, disabled.
...
CLK1 A/B
...
-
...
Not used, disabled.
...
CLK2 A/B
...
125 MHz
...
MGT reference clock 1.
...
CLK3A
...
-
...
Bank 34 clock input, default disabled, user clock.
...
CLK3B
...
-
...
Not used, disabled.
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D2 | Green | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted). |
Table 14: On-board LEDs.
Power and Power-On Sequence
...
Power Consumption
| Power Input Pin | Max Typical Current |
|---|---|
| VIN | TBD* |
| 3.3VINTBD* | TBD* |
Table 15: Power consumption.
* TBD - To Be Determined.
...
B2B Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Note |
|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage. |
| 3.3VIN | 13, 15 | - | Input | Supply voltage. |
| VCCIO13 | 9, 11 | - | Input | High range bank voltage. |
| VCCIO34 | - | 5 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
| VCCIO35 | - | 7, 9 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
| VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
| 1.8V | 39 | - | Output | Internal 1.8V voltage level. |
| DDR_PWR | - | 19 | Output | Internal 1.5V or 1.35V voltage level, depends on revision. |
| VREF_JTAG | 91 | Output | JTAG reference voltage (3.3V). |
Table 16: TE0715 power rails.
Bank Voltages
Bank | Schematic Name | Voltage | TE0715-xx-15 | TE0715-xx-30 |
|---|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | - | - |
| 501 | VCCO_MIO1_501 | 1.8V | - | - |
| 502 | VCCO_DDR_502 | 1.5V | - | - |
| 0 Config | VCCO_0 | 3.3V | - | - |
| 13 HR | VCCO_13 | User | HR: 1.2V to 3.3V | HR: 1.2V to 3.3V |
| 34 HR/HP | VCCO_34 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
| 35 HR/HP | VCCO_35 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
Table 17: TE0715 bank voltages.
Board to Board Connectors
...
| Module Variant | Zynq SoC | Temperature Range | B2B Connector Height |
|---|---|---|---|
| TE0715-04-15-1I | XC7Z015-1CLG485I | Industrial | 4.0 mm |
| TE0715-04-15-2I | XC7Z015-2CLG485I | Industrial | 4.0 mm |
| TE0715-04-30-1I | XC7Z030-1SBG485I | Industrial | 4.0 mm |
| TE0715-04-30-3E | XC7Z030-3SBG485E | Extended | 4.0 mm |
| TE0715-04-15-1I3 | XC7Z015-1CLG485I | Industrial | 2.5 mm |
| TE0715-04-30-1I3 | XC7Z030-1SBG485I | Industrial | 2.5 mm |
| TE0715-04-30-1C | XC7Z030-1SBG485C | Commercial | 4.0 mm |
Table 18: TE0715 variants currently in production.
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
| VBAT supply voltage | -1 | 6.0 | V | - |
| PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
| I/O input voltage for HR I/O banks | -0.4 | VCCO + 0.55 | V | - |
| I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | TE0715-xx-15 does not have HP banks. |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0 + 0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | °C | - |
| Storage temperature without the ISL12020MIRZ and 88E1512 | -55 | +100 | °C | - |
Table 19: TE0715 module absolute maximum ratings.
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
...
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.5 | 5.5 | V | ||
| 3.3VIN supply voltage | 3.135 | 3.465 | V | ||
| VBAT_IN supply voltage | 2.7 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 |
| I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 |
| I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Table 20: TE0715 module recommended operating conditions.
Operating Temperature Ranges
...
| Date | Revision | Notes | Link to PCN | Documentation Link |
|---|---|---|---|---|
| 2016-06-21 | 04 | Second production release | Click to see PCN | TE0715-04 |
| - | 03 | First production release | TE0715-03 | |
| - | 02 | Prototypes | TE0715-02 | |
| - | 01 | Prototypes |
Table 21: TE0715 module hardware revision history.
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
...
Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-06-07 | v.64 | Jan Kumann | Minor formatting |
| 2017-03-02 | v.59 | Thorsten Trenz | Corrected boot mode table |
| 2017-02-10 | v.58 | Thorsten Trenz | Corrected PLL initial delivery state |
| 2017-01-25 | v.55
| Jan Kumann | New block diagram. |
| 2017-01-14 | v.50 | Jan Kumann | Product revision 04 images added. Formatting changes and small corrections. |
| 2016-11-15 | v.45 | Thorsten Trenz | Added B2B Connector section. |
| 2016-10-18 | v.40 | Ali Naseri | Added table "power rails". |
| 2016-06-28 | v.38
| Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pin-out Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. |
| 2016-04-27 | v.33 | Thorsten Trenz, Emmanuel Vassilakis | Added table "Recommended Operating Conditions". Storage Temperature edited. |
| 2016-03-31 | v.10 | Philipp Bernhardt, Antti Lukats | Initial version. |
Table 22: Document change history.
Disclaimer
| Include Page | ||||
|---|---|---|---|---|
|
Boot mode pin descriptionReference clock signals.
Overview
Content Tools